10 Tier 2 & Tier 3 Practice

Additional problems organized by chapter, then by tier.

Chapter 2 — Logic Circuits

Tier 2 · Mid

2.43HardTier 2?R
Design a circuit with two outputs: $f_1 = \sum m(0,2,3,4,5,7)$ and $f_2 = \sum m(1,2,3,5,6,7)$ (3-variable). Find a minimum-cost shared-gate implementation.
Note — "shared-gate implementation" means: design one circuit that computes both $f_1$ and $f_2$ together, reusing common gates between them, and minimize the total cost (gate count + total input count across both outputs combined) instead of building two independent circuits.
2.44EasyTier 2?R
Using Boolean algebra, prove that $x + x \cdot y = x$ (absorption theorem).
2.45EasyTier 2?R
Draw a logic circuit using only NAND gates that implements the function $f = a \cdot b + c$.
2.46MediumTier 2?R
Write a structural Verilog module that implements $f = (a \cdot b) + (\overline{a} \cdot c)$ using gate-level primitives.
2.47EasyTier 2?R
Using a Venn diagram, verify that $x \cdot (y + z) = x \cdot y + x \cdot z$ (distributive law).
2.48MediumTier 2?R
Find the minimum POS expression for $f(a,b,c,d) = \prod M(0,1,4,5,9,11,15)$.
2.49EasyTier 2?R
What is the cost (number of gates + number of gate inputs) of the function $f = x_1 x_2 + \overline{x_1}\,x_3 + x_2 x_3$?
2.50MediumTier 2?R
Analyze the logic network: input signals pass through gates as follows — $g = \overline{a}$, $h = a \cdot b$, $f = g + h$. Derive the truth table and the simplified expression for $f$.

Tier 3 · Residual

2.51MediumTier 3?R
Explain the difference between structural and behavioral Verilog descriptions. Give a short example of each for the XOR function.
2.52MediumTier 3?R
Write a Verilog module that implements the function from exercise 2.5 using an assign statement. Write a simple testbench that applies all 16 input combinations.
2.53HardTier 3?R
A system has four sensors, each producing 0 or 1. An alarm must be raised when two or more sensors output 1. Derive the minimum SOP expression using a Karnaugh map.
2.54HardTier 3?R
Find the minimum-cost circuit using only two-input NAND gates for $f(x_1,x_2,x_3,x_4) = \sum m(0,1,2,3,4,6,8,9,12)$. Assume inputs are available in both true and complemented form.
2.55HardTier 3?R
Prove or disprove: $f = x_1 x_2 x_5 + x_1\overline{x_2}\,x_4 x_5 + \overline{x_1}\,x_2\overline{x_4}\,x_5 + x_1 x_2 x_3 x_4$ equals $g = x_2 x_3 x_4 + x_2\overline{x_3}\,\overline{x_4}\,x_5 + \overline{x_1}\,\overline{x_3}\,x_4 x_5 + x_1 x_2\overline{x_4}\,x_5$.

Chapter 3 — Number Representation & Arithmetic

Tier 2 · Mid

3.24HardTier 2?R
Derive the carry-lookahead equations for a 4-bit adder. Express $c_1, c_2, c_3, c_4$ in terms of generate ($g_i$) and propagate ($p_i$) signals.
3.25EasyTier 2?R
Find the 2's complement of the following 8-bit numbers: $01010101$, $11110000$, $10000000$.
3.26EasyTier 2?R
Convert the decimal numbers 0.625 and 0.3 to binary fractions (at least 8 bits after the binary point). Note which is exact and which is approximate.
3.27MediumTier 2?R
Prove that the XOR operation is associative: $x_i \oplus (y_i \oplus z_i) = (x_i \oplus y_i) \oplus z_i$.
3.28EasyTier 2?R
Encode the decimal number 947 in BCD (Binary-Coded Decimal).
3.29MediumTier 2?R
Add the BCD numbers $0110\;0111$ (67) and $0100\;0101$ (45). Show the correction step where 6 must be added.
3.30EasyTier 2?R
Write a Verilog module that adds two 8-bit numbers using the + operator and outputs a 9-bit result (including carry-out).
3.31MediumTier 2?R
Perform the subtraction $01110101 - 11010110$ in 8-bit 2's complement. Verify by converting to decimal.

Tier 3 · Residual

3.32EasyTier 3?R
Convert the following between octal, hexadecimal, and binary: $(752)_8$, $(B3D)_{16}$.
3.33HardTier 3?R
Determine the number of gates needed to implement an n-bit carry-lookahead adder assuming no fan-in constraints. Use AND, OR, and XOR gates.
3.34HardTier 3?R
What is the critical-path delay of an n-bit ripple-carry adder in terms of gate delays? Compare it with a carry-lookahead adder.
3.35HardTier 3?R
Design a hierarchical carry-lookahead adder using two 2-bit CLA blocks to build a 4-bit adder. Show the complete circuit with generate/propagate at both levels.
3.36HardTier 3?R
Write Verilog code for a 4×4 unsigned array multiplier. Use generate statements to create the partial product and addition logic. Verify with a testbench.

Chapter 4 — Combinational Logic

Tier 2 · Mid

4.48HardTier 2?R
Design an 8-to-1 multiplexer using only 2-to-1 multiplexers. How many 2-to-1 muxes are needed? Draw the tree structure.
4.49EasyTier 2?R
Using the Verilog conditional operator ? :, write a one-line assign statement that implements a 4-to-1 multiplexer.
4.50EasyTier 2?R
A demultiplexer routes one input to one of four outputs based on a 2-bit select signal. Write its truth table.
4.51MediumTier 2?R
Write a Verilog module for a 4-bit comparator using the relational operators <, ==, >.
4.52MediumTier 2?R
Write a Verilog function that takes a 4-bit BCD input and returns the corresponding 7-segment display output (7 bits).
4.53MediumTier 2?R
Use a for loop in Verilog to describe an 8-bit population count circuit (counts the number of 1s in an 8-bit input).
4.54MediumTier 2?R
Show how repeated application of Shannon's expansion can be used to derive all minterms of $f = w_2 + w_1 w_3 + \overline{w_1}\,w_3$.
4.55EasyTier 2?R
Explain the difference between casex and casez in Verilog. When would you use each?

Tier 3 · Residual

4.56MediumTier 3?R
Write a Verilog task that swaps two 8-bit values. Call this task from a module to sort three inputs in ascending order.
4.57MediumTier 3?R
Using multiplexers, implement the carry stage (stage 0) of a carry-lookahead adder. Show how $s_0$ and $c_1$ are generated.
4.58HardTier 3?R
Implement the function $f = w_1 w_2 + w_2 w_3 + \overline{w_1}\,\overline{w_2}\,w_3$ using Shannon's expansion to build a multilevel circuit. Compare its cost with the direct SOP implementation.
4.59HardTier 3?R
Design a parameterized $n$-to-$2^n$ decoder in Verilog using the generate construct. Verify for n = 3.
4.60HardTier 3?R
Implement a cascadable 4-bit magnitude comparator with cascade inputs (Agtb_in, Aeqb_in, Altb_in). Show how two can be chained to compare 8-bit numbers.

Chapter 5 — Flip-Flops & Sequential

Tier 2 · Mid

5.36HardTier 2?R
Design a 4-bit counter with parallel load capability: when Load=1, the counter loads a 4-bit value D; otherwise it counts up. Include an asynchronous reset. Write the Verilog code.
5.37EasyTier 2?R
Write the characteristic table and characteristic equation for a JK flip-flop.
5.38MediumTier 2?R
Design a 4-bit serial-in, serial-out shift register using D flip-flops. Draw the circuit and trace the output when the input sequence is 1,0,1,1.
5.39EasyTier 2?R
What is the counting sequence of a 4-bit ring counter initialized to 1000?
5.40MediumTier 2?R
What is the counting sequence of a 4-bit Johnson counter initialized to 0000? How many unique states does it pass through?
5.41MediumTier 2?R
Write Verilog code for an 8-bit parallel-access shift register that can shift left, shift right, load in parallel, or hold, controlled by a 2-bit mode input.
5.42MediumTier 2?R
Design a BCD counter (counts 0000 to 1001, then wraps to 0000) using synchronous reset. Write the Verilog code.
5.43EasyTier 2?R
Write Verilog code for a simple 4-bit up counter with asynchronous reset using always @(posedge Clock or negedge Resetn).

Tier 3 · Residual

5.44MediumTier 3?R
Given a 4-bit shift register with input Sin and parallel outputs Q[3:0], write a Verilog module that detects when the serial pattern 1011 has been completely shifted in.
5.45HardTier 3?R
Design a modulo-6 counter (counts 0 through 5) using D flip-flops. Derive the next-state logic using Karnaugh maps and draw the complete circuit.
5.46HardTier 3?R
A flip-flop has setup time tsu = 2 ns, hold time th = 1 ns, and propagation delay tcQ = 3 ns. The combinational logic between two flip-flops has a delay of 5 ns. What is the maximum clock frequency? What if there is a clock skew of 0.5 ns?
5.47HardTier 3?R
A linear-feedback shift register (LFSR) has the feedback polynomial x³ + x + 1. Starting from 001, trace all states in the sequence. Is this a maximal-length sequence?
5.48HardTier 3?R
Design a frequency divider that takes a clock input and produces an output clock at 1/6 of the input frequency with a 50% duty cycle. Give the Verilog code.

Chapter 6 — Finite State Machines

Tier 2 · Mid

6.31HardTier 2?R
Derive the state diagram for an FSM that detects either 1001 or 1111 patterns on input w (overlapping allowed). Verify with the sequence w: 010111100110011111.
6.32MediumTier 2?R
What is the formal model of a finite state machine? Define the 5-tuple (S, I, O, δ, λ) and explain each component.
6.33EasyTier 2?R
Given a sequential circuit with two D flip-flops and combinational logic, analyze the circuit: derive the state table and draw the state diagram from the given next-state equations D₁ = x ⊕ Q₂ and D₂ = Q₁.
6.34MediumTier 2?R
Design an arbiter FSM that grants access to one of two requestors (r₁, r₂). The arbiter has outputs g₁ and g₂ (grants). It should give priority to r₁ when both request simultaneously.
6.35EasyTier 2?R
What are the advantages of using ASM charts over state diagrams for complex designs?
6.36MediumTier 2?R
List and describe the six basic steps for designing a synchronous sequential circuit as outlined in the textbook.
6.37MediumTier 2?R
Explain how specifying state encoding in Verilog (e.g., using (* synthesis, encoding = "one-hot" *)) affects the synthesized hardware. Compare binary, Gray, and one-hot for an 8-state FSM.
6.38HardTier 2?R
Design a modulo-8 counter using the sequential circuit design approach with D flip-flops. Derive the state table, state assignment, and next-state logic equations using K-maps.

Tier 3 · Residual

6.39HardTier 3?R
Repeat exercise 6.38 using JK flip-flops. Compare the total gate count with the D flip-flop implementation.
6.40HardTier 3?R
A sequential circuit has two inputs w₁ and w₂. It outputs z=1 when w₁=w₂ for four consecutive clock cycles. Derive the state diagram and Verilog code.
6.41HardTier 3?R
Design a serial adder FSM that adds two n-bit numbers presented one bit at a time (LSB first). Design both Moore and Mealy versions and compare the timing of the output.
6.42HardTier 3?R
Convert the following Mealy FSM to an equivalent Moore FSM: States {A,B,C}, Input w, Output z. Transitions: A→(w=0:A/0, w=1:B/0), B→(w=0:A/0, w=1:C/1), C→(w=0:A/0, w=1:C/1). Show all steps.
6.43HardTier 3?R
Design a Moore FSM that outputs 1 when either 110 or 101 patterns are detected (overlapping). Derive the minimal state table, state assignment, and complete implementation.

Chapter 7 — Datapaths & Controllers

Tier 2 · Mid

7.4EasyTier 2?R
What is switch debouncing? Why is it necessary, and describe one hardware-based and one software-based approach to handle it.
7.8MediumTier 2?R
Design a simple GCD (Greatest Common Divisor) calculator using the Euclidean algorithm. Draw the ASM chart and identify the datapath components needed.
7.9MediumTier 2?R
Write Verilog code for a parameterized n-bit counter with enable, synchronous load, and synchronous reset. Instantiate it as a 16-bit counter.
7.3MediumTier 2?R
Draw an ASM chart for a circuit that computes the arithmetic mean of four 8-bit unsigned numbers loaded sequentially.
7.6MediumTier 2?R
The simple processor supports the operations: Load, Move, Add, Sub. Write microinstructions (control signals) for each operation.
7.11HardTier 2?R
Write complete Verilog code for a bit-counting circuit that counts the number of 1s in an 8-bit register. Use a datapath with a shift register and a counter, controlled by an FSM.
7.13HardTier 2E?R
Design a bit-counting circuit that, given an $n$-bit unsigned input loaded into a shift register, counts the number of 1s in the input. Provide the datapath (shift register, counter, control signals) and an ASM chart for the controlling FSM, then write Verilog code for the complete circuit.
7.14HardTier 2E?R
Design a shift-and-add multiplier for two $n$-bit unsigned numbers. Use a multiplicand register, a partial-product accumulator, and a shift register for the multiplier. Provide the ASM chart for the control FSM and write Verilog code for both the datapath and the controller.
7.16HardTier 2E?R
Design a circuit that computes the arithmetic mean of $k$ unsigned $n$-bit numbers presented sequentially on an input bus. Provide a datapath with an accumulator and a divide-by-$k$ operation, an ASM chart, and Verilog code.
7.17HardTier 2E?R
Design a hardware sort circuit that sorts $k$ unsigned $n$-bit numbers stored in a small register file into ascending order, using a selection-sort or bubble-sort style algorithm. Provide the datapath, ASM chart for the controller, and Verilog code for the complete sorter.
7.18HardTier 2?R
Design a complete system that reads 4-bit values from an input port, stores up to 8 values in a register file, and computes their sum and average. Give the ASM chart and Verilog code.
7.19MediumTier 2?R
Write Verilog code that uses a tri-state buffer (assign bus = enable ? data : 8'bz;) to connect two modules to a shared 8-bit bus.
7.20MediumTier 2?R
Design a sorting network that sorts three 4-bit unsigned numbers in ascending order using compare-and-swap units. Draw the block diagram.
7.21EasyTier 2?R
What is the difference between Moore-type and Mealy-type outputs in an ASM chart? Draw a small ASM chart illustrating both.
7.22EasyTier 2?R
What is a synchronizer circuit? Draw a two-flip-flop synchronizer and explain why a single flip-flop is insufficient.
7.23MediumTier 2?R
A divider uses the repeated-subtraction method. Write pseudo-code for this approach and compare the number of cycles needed versus the restoring divider for 255 ÷ 7.
7.24MediumTier 2?R
How many clock cycles does a 4-bit shift-and-add multiplier need to complete one multiplication? What about an 8-bit version?
7.25MediumTier 2?R
Design a debouncing circuit for a mechanical pushbutton using an SR latch and two pull-up resistors. Draw the circuit and explain the operation.

Tier 3 · Residual

7.26MediumTier 3?R
Explain why clock distribution is critical in high-speed digital systems. What techniques can be used to minimize clock skew?
7.27HardTier 3?R
Design a restoring divider that divides an 8-bit dividend by a 4-bit divisor. Show the datapath and ASM chart for the control unit.
7.28HardTier 3?R
Write Verilog code for the shift-and-add multiplier from exercise 7.12. Include a testbench that multiplies 13 × 11 and verifies the result is 143.
7.29HardTier 3?R
Modify the shift-and-add multiplier to handle signed numbers (2's complement). What changes are needed in the datapath and control?
7.30HardTier 3?R
Design a UART transmitter that sends 8-bit data with 1 start bit and 1 stop bit. Draw the ASM chart, identify datapath components, and write Verilog code.

Chapter 8 — Optimization

Tier 2 · Mid

8.5EasyTier 2?R
Why are Karnaugh maps impractical for functions with more than 5–6 variables? What alternatives does the chapter present?
8.9MediumTier 2?R
What is an ROBDD (Reduced Ordered BDD)? What two reduction rules are applied, and why is canonical form important for verification?
8.20MediumTier 2E?R
Analyze a NAND-only circuit (Figure 8.14a) by labeling internal nodes $P_1, P_2, P_3$ and propagating bubbles via DeMorgan's theorem until an equivalent AND/OR circuit is obtained. Show that the function is $f = x_1 x_2 x_4 + \overline{x_3}\, x_4 + \overline{x_5}$.
Context: Example 8.8 — analyzing a NAND-only circuit by bubble-pushing

Figure 8.14a is a chain of four 2-input NAND gates. Each gate output gets a fresh inversion bubble, so analysis is easier if we push bubbles around using DeMorgan: $\overline{AB} = \overline{A} + \overline{B}$.

x1 x2 x3 x4 x5 NAND P1 NAND P2 NAND P3 NAND f Figure 8.14a — NAND-only circuit

Direct trace (NAND outputs). Each $P_i$ is the NAND of its two inputs:

$P_1 = \overline{x_1 x_2}, \quad P_2 = \overline{P_1 \cdot x_3}, \quad P_3 = \overline{P_2 \cdot x_4}, \quad f = \overline{P_3 \cdot x_5}.$

Bubble-push from the output. Apply DeMorgan to $f$, then unwind:

$f = \overline{P_3 \cdot x_5} = \overline{P_3} + \overline{x_5} = (P_2 \cdot x_4) + \overline{x_5}.$

$P_2 \cdot x_4 = \overline{P_1 \cdot x_3}\cdot x_4 = (\overline{P_1} + \overline{x_3})\,x_4 = (x_1 x_2 + \overline{x_3})\,x_4.$

Therefore $f = (x_1 x_2 + \overline{x_3})\,x_4 + \overline{x_5} = x_1 x_2 x_4 + \overline{x_3}\, x_4 + \overline{x_5}.$

Why this works (the bubble-pushing rule). A NAND can always be redrawn as an OR with both inputs inverted: $\overline{AB} = \overline{A} + \overline{B}$. Cascaded NANDs alternately propagate AND/OR layers, with bubbles cancelling on internal wires when they meet (two bubbles on the same wire ≡ no bubble). After cancellation, surviving bubbles end up only on the primary inputs that lit up the inversions — here, $x_3$ and $x_5$ — yielding the AND-OR equivalent in Figure 8.14c.

Counting the survivors. Travel from $f$ back to each input. Count NAND-output bubbles on the path: an even count cancels, an odd count leaves the input complemented. For $x_1, x_2$: two bubbles (at NAND1 and NAND4) — wait, NAND1 output bubble is on the output side, then it enters NAND2 which has no input bubble; bubbles only appear at NAND outputs, and every NAND output is consumed by the next NAND. So pair-cancellation between NAND1 output bubble and the implicit DeMorgan-redrawn NAND2 (= AND with input bubbles) yields a clean AND. Trace each input: $x_1, x_2, x_4$ → no surviving bubble; $x_3, x_5$ → one surviving bubble each (complemented). Matches the algebraic result above.

— example 8.8
8.26MediumTier 2E?R
Apply the $\star$-product (cubical) operation to the cover $C_0=\{000, 001, 010, 011, 111\}$ of a 3-variable function. Generate $C_1, C_2, \ldots$ until convergence and confirm the prime implicants are $\{x11, 0xx\}$.
8.2MediumTier 2?R
Implement the logic circuit f = ac + ad + bc + bd + e using only NAND gates.
8.8MediumTier 2?R
Use algebraic division to extract common sub-expressions from f = abd + abe + acd + ace. Show the factored form.
8.11MediumTier 2?R
Construct the BDD for a 2-to-1 multiplexer function f = s·d₁ + s̄·d₀ with ordering s < d₀ < d₁. Then try ordering d₀ < d₁ < s. Compare sizes.
8.16MediumTier 2E?R
Implement the XOR function $f = x_1 \oplus x_2$ using only NAND gates. First derive a five-NAND realization from the SOP form, then apply functional decomposition with $g = x_1 \uparrow x_2$ to obtain a four-NAND implementation.
8.22MediumTier 2E?R
Given the BDD for a 3-variable function with input order $(x_2, x_1, x_3)$ in Figure 8.22d, swap the positions of nodes $x_1$ and $x_2$ to obtain a BDD with input order $(x_1, x_2, x_3)$. Use a small truth table to track the destinations of edges crossing the swap boundary.
8.24HardTier 2E?R
Apply the Quine-McCluskey tabular method to find all prime implicants of the function $f(x_1,\ldots,x_4) = \sum m(0,2,5,6,7,8,9,13) + D(1,12,15)$. Then construct the prime-implicant cover table, apply row and column dominance, and select a minimum-cost cover.
8.28MediumTier 2E?R
Use the $\#$-operation to determine which of the prime implicants $\{x11, 0xx\}$ for the function in Figure 2.56 are essential. Show the explicit $\#$-computations and explain the significance of a non-empty result.— example 8.14
8.32HardTier 2E?R
Use functional decomposition (with subfunctions of $x_3$ and $x_4$) on $f = x_1 x_3 + x_1 x_4 + x_2 x_4 + x_2 x_3 + \overline{x_1}\overline{x_2}\overline{x_3}\overline{x_4}$. Show step-by-step that $f$ can be simplified to $f = \overline{x_3}\overline{x_4} + (x_1 + x_2)(x_3 + x_4)$.
8.38HardTier 2E?R
Two cascaded 4-input LUTs can implement a 7-variable function $f(x_1,\ldots,x_7) = h[g(x_1,\ldots,x_4), x_5, x_6, x_7]$. Show that this structure can implement $f = x_1 x_2 x_3 x_4 x_5 x_6 x_7$ and $f = x_1 + x_2 + \cdots + x_7$, but argue that there exist 7-variable functions that cannot be realized with just two 4-LUTs.
8.6MediumTier 2?R
Find the simplest realization of f(x₁,...,x₄) = Σm(0,3,4,7,9,10,13,14) assuming gates have a maximum fan-in of 2.
8.10MediumTier 2?R
Explain how technology mapping transforms a technology-independent netlist into one that uses specific library gates (e.g., from a standard cell library).
8.13MediumTier 2E?R
Design a minimum-cost combined circuit for two functions $f_1$ and $f_2$ of four variables, where $f_1$ asserts when at least one of $x_1, x_2$ is 1 and both $x_3, x_4$ are 1, or when $x_1=x_2=0$ and at least one of $x_3, x_4$ is 1; and $f_2 = (x_1+x_2)(x_3+x_4)$. Use factoring to share common subexpressions across both outputs.
8.14MediumTier 2E?R
Apply functional decomposition to the 4-variable function $f = x_1 x_3 \overline{x_4} + x_1 \overline{x_3} x_4 + \overline{x_2} x_3 \overline{x_4} + \overline{x_2}\overline{x_3} x_4$. Identify a 2-variable subfunction $g(x_3,x_4)$ that appears in multiple columns of the K-map and rewrite $f$ as a multilevel circuit using $g$.
8.15HardTier 2E?R
A 5-variable function $f$ is given as a Karnaugh map (Figure 8.8a). By examining the rows and columns, find subfunctions $g(x_1,x_2,x_5)$ and $k(x_3,x_4)$ such that $f = h(g,k)$, then realize $f$ as a multilevel circuit and compare its cost to the minimum-cost SOP form.
Context: Example 8.3 — functional decomposition by inspecting K-map rows

The K-map of $f(x_1,x_2,x_3,x_4,x_5)$ — two 4×4 panels (one per value of $x_5$); columns indexed by $x_1 x_2$, rows by $x_3 x_4$:

$x_5 = 0$
$x_3 x_4$ \ $x_1 x_2$00011110
001000
01 ←0111
111000
10 ←0111
$x_5 = 1$
$x_3 x_4$ \ $x_1 x_2$00011110
000000
01 ←1111
110000
10 ←1111

Step 1 — observe row patterns. Each row depends only on $(x_1, x_2, x_5)$. Two distinct patterns appear:

  • Rows 01 and 10 (marked ←): "1 wherever any of $x_1, x_2, x_5$ is 1" → $g(x_1,x_2,x_5) = x_1 + x_2 + x_5$
  • Rows 00 and 11: complementary pattern, 1 only at $x_1=x_2=x_5=0$ → $\overline{g}$

Step 2 — identify which rows have which pattern. The "←" rows ($x_3 x_4 = 01, 10$) are exactly the cases where $x_3 \ne x_4$. So let $k(x_3, x_4) = x_3 \oplus x_4$.

Then: $k=1$ rows (01, 10) → $f = g$; $k=0$ rows (00, 11) → $f = \overline{g}$.

Step 3 — combine.

$$f = k\cdot g + \overline{k}\cdot \overline{g} = \overline{g \oplus k} = g \odot k$$

So $h(g, k) = g \odot k$ (XNOR).

Decomposed circuit:

x₁ x₂ x₅ OR g x₃ x₄ XOR k XNOR h(g,k) f

Cost comparison:

RealizationGatesTotal inputsCost
Multilevel: $f = g \odot k$, $g = x_1+x_2+x_5$, $k = x_3 \oplus x_4$3 (OR3, XOR2, XNOR2)3+2+2 = 710
Direct minimum-cost SOP (~16 ones, no large rectangles)~7–10 ANDs + 1 OR~25–30~35+

The decomposition pays off because the two K-map row patterns depend on disjoint variable sets. The textbook lesson: spatial regularity in the K-map (rows or columns repeating) signals an opportunity to factor out a subfunction.

— example 8.3
8.17MediumTier 2E?R
Convert the four-level AND-OR circuit in Figure 8.10a into (a) an equivalent NAND-only circuit and (b) an equivalent NOR-only circuit, by inserting bubble pairs and absorbing them into gates.
Context: Example 8.5 — bubble-pair conversion of multi-level AND/OR circuits

The trick. Add two inverters (a "bubble pair") on a wire — logically they cancel, so the circuit's function is unchanged. Then absorb each bubble into the gate at one end of the wire, converting AND/OR gates into NAND/NOR gates by DeMorgan's theorem.

DeMorgan equivalences (the engine):

$$\overline{a \cdot b} = \overline{a} + \overline{b} \qquad \overline{a + b} = \overline{a} \cdot \overline{b}$$

Reading this as gate symbols:

Original gate= equivalentUse to build
AND with output bubbleNANDNAND-only
OR with input bubblesNAND (by DeMorgan)NAND-only
OR with output bubbleNORNOR-only
AND with input bubblesNOR (by DeMorgan)NOR-only

The conversion recipe. Walk every wire in the circuit and add a bubble-pair so that each gate has the bubble pattern it needs:

  • For NAND-only: every AND gets an output bubble; every OR gets input bubbles. When two adjacent gates share a wire, their bubbles meet in the middle and cancel — that wire becomes a clean signal again. Every gate now has the right bubble pattern to be a NAND.
  • For NOR-only: every OR gets an output bubble; every AND gets input bubbles. Same wire-by-wire cancellation argument — every gate is now a NOR.

What's left over: primary inputs and the final output may have an unmatched bubble that doesn't pair up with another gate's bubble. Each leftover bubble is implemented as a separate inverter — which can be a NAND (or NOR) with its inputs tied together:

$$\text{NAND}(x, x) = \overline{x \cdot x} = \overline{x} \qquad \text{NOR}(x, x) = \overline{x + x} = \overline{x}$$

So the final circuit is uniformly NAND (or NOR) gates, no other gate types needed.

Step-by-step on the textbook's 4-level circuit:

  1. Start with Figure 8.10a (alternating AND/OR/AND/OR levels with inputs $x_1$–$x_7$).
  2. Insert bubble pairs on every internal wire so every AND has an output bubble + every OR has input bubbles (Figure 8.10b shows these in blue).
  3. Absorb bubbles into gates: every gate symbol now matches NAND.
  4. Leftover bubbles at inputs $x_1, x_5, x_6, x_7$ and at output $f$ become NAND-as-inverter cells.
  5. Result: Figure 8.10c — a NAND-only circuit functionally identical to the original.

For NOR-only conversion (Figure 8.11), swap the rules: ORs get output bubbles, ANDs get input bubbles. Leftover bubbles at $x_2, x_3, x_4$ become NOR-as-inverter cells (Figure 8.11b).

Tiny illustration of the bubble cancellation:

Original: a, b → AND OR → f + pair: a, b → NAND ↳ bubbles cancel NAND → f

The two bubbles on the middle wire cancel; the AND with output-bubble is a NAND; the OR with input-bubbles is also a NAND (by DeMorgan). Same function, all-NAND realization.

— example 8.5
8.18MediumTier 2E?R
Determine the function $f$ implemented by the multilevel AND-OR circuit in Figure 8.12 by labeling internal nodes and tracing from output to inputs. Express $f$ in two-level SOP form and compute its gate cost.
Context: Example 8.6 — analyzing a multilevel circuit by node labeling

The strategy: label every internal wire with a name ($P_1, P_2, \ldots$), write the function at each gate output, then substitute back to get $f$ in terms of the primary inputs.

Figure 8.12 — the circuit (4 levels deep, AND/OR alternation, inputs $x_1$–$x_7$):

x₁ x₂ x₃ x₄ x₅ x₆ x₇ AND P₁ OR P₃ OR P₂ AND P₄ OR P₅ AND f

Trace from inputs forward:  $P_1 = x_2 x_3$,  $P_2 = x_5 + x_6$,  $P_3 = x_1 + P_1 = x_1 + x_2 x_3$,  $P_4 = x_4 P_2 = x_4(x_5+x_6)$,  $P_5 = P_4 + x_7 = x_4(x_5+x_6) + x_7$,  giving $f = P_3 \cdot P_5 = (x_1 + x_2 x_3)\bigl(x_4(x_5+x_6) + x_7\bigr)$.

Two-level SOP form (distributive law):  $f = x_1 x_4 x_5 + x_1 x_4 x_6 + x_1 x_7 + x_2 x_3 x_4 x_5 + x_2 x_3 x_4 x_6 + x_2 x_3 x_7$.

6 product terms, total 25 input literals (3+3+2+4+4+3) plus the 6-input OR.

Cost comparison:

FormGatesTotal inputsCostDelay
Multilevel (Figure 8.12)6 (P₁,P₂ + P₃,P₄ + P₅ + f)2+2+2+2+2+2 = 12184 gate-delays
Two-level SOP7 (six ANDs + one OR)3+3+2+4+4+3 + 6 = 25322 gate-delays

Trade-off: the multilevel form has lower gate cost but more depth (slower); the two-level form is faster but more expensive. Multilevel optimization is mostly an area-vs-speed knob.

— example 8.6
8.19MediumTier 2E?R
For the multilevel circuit derived in Example 8.3 (with the XOR/XNOR replaced by SOP equivalents), label the internal nodes and derive the SOP expression for the output by tracing the circuit. Verify it matches the original specification.— example 8.3
8.21MediumTier 2E?R
Analyze a circuit consisting of a mixture of NAND and NOR gates (Figure 8.15) by labeling intermediate nodes $P_1$ to $P_4$ and applying DeMorgan's theorem. Reduce the result to $f = x_1 x_5 + x_2 x_5 + \overline{x_3} x_5 + x_4 x_5$.— example 8.9
8.23HardTier 2E?R
Construct the BDD for $f = x_1 x_3 + x_1 x_4 + x_2 x_4 + x_2 x_3 + \overline{x_1}\overline{x_2}\overline{x_3}\overline{x_4}$ with input order $x_1, x_2, x_3, x_4$, by applying Shannon's expansion successively on $x_1$ and $x_2$ and merging identical subgraphs. Use the BDD to derive a multilevel SOP expression.
8.25HardTier 2E?R
For $f(x_1,\ldots,x_4) = \sum m(0,3,10,15) + D(1,2,7,8,11,14)$, generate all prime implicants tabularly. Build the cover table, observe that there are no essential prime implicants and no row/column dominance, and use branching to find a minimum-cost cover.
8.27HardTier 2E?R
Given the initial cover $C_0=\{0101, 1101, 1110, 011x, x01x\}$ for a 4-variable function, use the $\star$-product operation to derive all prime implicants. List the resulting product terms in algebraic form.
8.29HardTier 2E?R
For the prime-implicant set $P=\{x01x, x101, 01x1, 0x1x, xx10\}$ of a 4-variable function with no don't-cares, use the $\#$-operation to identify all essential prime implicants. Show the cube that demonstrates each essential implicant.
8.30HardTier 2E?R
Apply the complete cubical minimization procedure ($\star$-product to find prime implicants, $\#$-operation to find essential ones, then branching) to the 5-variable function $f(x_1,\ldots,x_5)=\sum m(0,1,4,8,13,15,20,21,23,26,31)+D(5,10,24,28)$. Provide the minimum-cost SOP expression.
8.33MediumTier 2E?R
Construct a BDD for $f = x_1 x_3 + x_2 x_4$ with input order $x_1, x_2, x_3, x_4$ by applying Shannon's expansion first on $x_1$ and then on $x_2$ within one of the cofactors.
8.34MediumTier 2E?R
Given the BDD for $f = x_1 x_3 + x_2 x_4$ with order $x_1, x_2, x_3, x_4$, derive a BDD with input order $x_1, x_3, x_2, x_4$ by swapping the inner $x_2$ and $x_3$ levels. Use a truth table to track the destinations of edges crossing the swap boundary.
8.35HardTier 2E?R
Use the tabular method to derive a minimum-cost SOP expression for $f(x_1,\ldots,x_4) = \overline{x_1}\overline{x_3}\overline{x_4} + \overline{x_3}x_4 + x_1\overline{x_2}x_4 + x_1\overline{x_2}\overline{x_3}x_4$ with don't-cares $D=(9,12,14)$. Show all generated cubes and the cover-table reduction.
8.36HardTier 2E?R
Use the $\star$-product operation to find all prime implicants of $f(x_1,\ldots,x_4) = \overline{x_1}\overline{x_3}\overline{x_4} + \overline{x_3}x_4 + x_1\overline{x_2}x_4 + x_1\overline{x_2}\overline{x_3}x_4$ with don't-cares $D=(9,12,14)$. Show the successive covers $C_0, C_1, C_2, \ldots$ until convergence.
8.37HardTier 2E?R
For the function in Examples 8.23 and 8.24, compare three implementation strategies: (a) minimum-cost SOP, (b) minimum-cost POS, and (c) a multilevel factored realization. Compute the gate-and-input cost of each and discuss the area-vs-delay trade-off.
Context: the function from Examples 8.23 / 8.24

The function:

$$f(x_1,x_2,x_3,x_4) = \sum m(0,1,3,4,7,11,13,15) + D(9,12,14)$$

K-map (4-variable, columns $x_3 x_4$, rows $x_1 x_2$, $d$ = don't-care):

$x_1 x_2$ \ $x_3 x_4$00011110
001 (m₀)1 (m₁)1 (m₃)0
011 (m₄)01 (m₇)0
11$d$ (m₁₂)1 (m₁₃)1 (m₁₅)$d$ (m₁₄)
100$d$ (m₉)1 (m₁₁)0

Example 8.23 uses the Quine–McCluskey tabular method to derive a minimum-cost SOP. The selected cover is $C = \{0x00,\ x0x1,\ xx11,\ 1xx1\}$, giving

$$f_\text{SOP} = \overline{x_1}\,\overline{x_3}\,\overline{x_4} + \overline{x_2}\,x_4 + x_3\,x_4 + x_1\,x_4$$

Example 8.24 uses the *-product operation on the same function and derives the full set of prime implicants $P = \{x_1\overline{x_3}\overline{x_4},\ \overline{x_3}\overline{x_4},\ \overline{x_1}\overline{x_2}\overline{x_3},\ \overline{x_2}x_3\overline{x_4},\ \overline{x_2}x_4,\ x_1 x_4,\ x_1 x_2\}$ — confirming the same minimum cover from a different algorithm.

What problem 8.37 asks: compute three realizations of this same function and compare costs.

(a) Minimum-cost SOP (from Example 8.23):

$$f = \overline{x_1}\,\overline{x_3}\,\overline{x_4} + \overline{x_2}\,x_4 + x_3\,x_4 + x_1\,x_4$$

Gates: 4 ANDs (3-input × 1, 2-input × 3) + 1 OR (4-input). Inputs: $3+2+2+2 = 9$ (AND) + 4 (OR) = 13. Cost = 5 gates + 13 inputs = 18.

(b) Minimum-cost POS — derive from the off-set ($f=0$ at minterms 2, 5, 6, 8, 10; with D=9,12,14 used to enlarge product groups). K-map grouping of zeros yields the maxterm cover, e.g.

$$f_\text{POS} = (x_2 + x_3 + x_4)\,(\overline{x_1} + x_4)\,(\overline{x_2} + x_4 + \overline{x_3})$$

(Exact cover depends on don't-care assignment; this is one valid minimum cover.) Gates: 3 ORs (3-input × 3) + 1 AND (3-input). Inputs: $3+3+3 = 9$ (OR) + 3 (AND) = 12. Cost = 4 gates + 12 inputs = 16.

(c) Multilevel factored realization — start from the SOP and factor out the common literal $x_4$:

$$f = \overline{x_1}\,\overline{x_3}\,\overline{x_4} + x_4\,(\overline{x_2} + x_3 + x_1)$$

Gates: 1 AND3 ($\overline{x_1}\overline{x_3}\overline{x_4}$), 1 OR3 ($\overline{x_2}+x_3+x_1$), 1 AND2 ($x_4 \cdot $ above OR), 1 OR2 (final). Inputs: $3 + 3 + 2 + 2 = 10$. Cost = 4 gates + 10 inputs = 14.

Comparison:

FormGatesInputsCostDelay
(a) Min SOP513182 (AND→OR)
(b) Min POS412162 (OR→AND)
(c) Multilevel factored410143 (OR→AND→OR)

Trade-off: SOP and POS are two-level — fastest at 2 gate-delays — but pay in gate count. Multilevel factored cuts cost by ~22% but adds one extra gate-delay because the signal traverses an extra logic level. Whether the multilevel form wins depends on the technology timing budget: in slow-clock FPGA fabric, area savings dominate; in critical-path ASIC datapaths, the two-level form's depth advantage may matter more.

— example 8.23
8.39HardTier 2?R
Apply the Quine-McCluskey method to a 5-variable function: f = Σm(0,2,3,5,7,8,10,11,14,15,24,26,27,29,31). Find all prime implicants and a minimum cover.
8.40MediumTier 2?R
Implement the same circuit from 8.2 using only NOR gates.
8.41MediumTier 2?R
Explain the cubical representation of logic functions. Represent the function f = x̄₁x₂ + x₁x̄₃ as a set of cubes.
8.42MediumTier 2?R
Given f = x₃x₅ + x₁x₂x₄ + x̄₁x₂x̄₄ + x₁x̄₃x₄ + x₁x₃x̄₄ + x₁x̄₂x₅ + x̄₁x₂x₅, derive a minimum-cost multilevel circuit.
8.43MediumTier 2?R
Derive the minimum-cost SOP implementation and the minimum-cost factored form for f(x₁,...,x₄) = Σm(4,7,8,11) + D(12,15). Compare costs.
8.44EasyTier 2?R
Define the terms: literal, cube, cover, prime implicant, essential prime implicant in the context of cubical representation.
8.45MediumTier 2?R
In the Quine-McCluskey method, explain the role of the "don't combine" check mark and how the prime implicant chart is used to select the final cover.
8.46MediumTier 2?R
Why is variable ordering important in BDDs? For the function f = x₁x₂ + x₃x₄ + x₅x₆, which ordering would you expect to produce a smaller BDD: interleaved (x₁

Tier 3 · Residual

8.47HardTier 3?R
Complete exercise 8.3 by constructing the prime implicant chart and finding a minimum cover.
8.48HardTier 3?R
Show that the BDD for an n-bit adder's carry-out is polynomial in n with one variable ordering but exponential with another. Demonstrate for n=3.
8.49HardTier 3?R
Find the minimum-cost circuit for f(x₁,...,x₄) = Σm(0,4,8,13,14,15) assuming inputs are available in uncomplemented form only. Use functional decomposition.
8.50HardTier 3?R
Given a standard cell library with 2-input NAND (cost 2), 2-input NOR (cost 2), inverter (cost 1), and 3-input NAND (cost 3), map the function f = ab + cd to minimize total cost.
8.51HardTier 3?R
Analyze the multilevel circuit: t₁ = a + b, t₂ = c·d, t₃ = t₁·e, f = t₂ + t₃. Derive the flattened SOP expression, then re-factor for minimum cost with a fan-in constraint of 2.

Chapter 9 — Asynchronous Circuits

Tier 2 · Mid

9.7MediumTier 2?R
For the merged flow table, explain the concepts of "compatible states" and "merger diagram." How is the merger diagram used to determine which states can share a row?
9.11MediumTier 2?R
What is an essential hazard? How does it differ from static and dynamic hazards? Can it be eliminated by adding redundant gates?
9.13MediumTier 2E?R
Analyze the gated D latch as an asynchronous sequential circuit. Derive the next-state expression $Y = CD + \overline{C}y$, the excitation table, the flow table, and the corresponding state diagram, treating the clock $C$ as one of the inputs.
9.18HardTier 2E?R
Design a simple two-device asynchronous arbiter using handshake signaling. Inputs are request signals $r_1, r_2$ and outputs are grant signals $g_1, g_2$. Provide a Moore state diagram with three states (idle, granted-1, granted-2), an extra unstable state to avoid a diagonal transition, and the modified flow table.
9.2MediumTier 2?R
Analyze the following asynchronous circuit: two cross-coupled NOR gates with external inputs x₁ and x₂. Derive the flow table identifying all stable and unstable states.
9.10MediumTier 2?R
Compare the advantages and disadvantages of synchronous vs. asynchronous design in terms of speed, power, testability, and design effort.
9.16HardTier 2E?R
Design a serial parity generator as an asynchronous Moore FSM with input $w$ and output $z$ such that $z=1$ if an odd number of pulses has appeared on $w$. Use four states to handle both edges of each pulse, choose a race-free state assignment with Hamming distance 1, and derive the next-state and output expressions.
9.22HardTier 2E?R
Reduce the 8-row flow table of Figure 9.43 to a 2-state Mealy FSM by applying the partitioning procedure followed by row merging. Show the merger diagram and the resulting reduced flow table.
Context: Example 9.10 — 8-row primitive table reduced to 2-state Mealy FSM

Setup. Figure 9.43 is an 8-row primitive flow table for an asynchronous Moore-like FSM. Inputs $w_2 w_1$, rows $A$–$H$, output $z$ varies per row. The dramatic claim: this 8-row table reduces all the way down to just 2 states via partitioning + merger, but the result is a Mealy FSM (some output depends on input not just state).

Stage 1 — Partitioning. Group by output and refine by next-state successors:

$$P_1 = (AF)(BEG)(C)(D)(H) \qquad P_2 = (AF)(BE)(G)(C)(D)(H) \qquad P_3 = P_2$$

So the partitioning step proves $A \equiv F$ and $B \equiv E$. Replace $F$ with $A$ and $E$ with $B$ → 6-row table (Figure 9.44 in the textbook):

State$w_2w_1$=00=01=10=11$z$
AABC0
BABH0
CACH0
DDGC1
GDGH0
HGCH1

Stage 2 — Merger diagram. Build a graph where each row is a vertex and each compatible pair (no conflicting next-state entries; Mealy-output compatibility) is an edge. From Figure 9.45:

  • $A$, $B$, $C$ form a clique → can all merge into a single new state (call it $A$)
  • $D$, $G$, $H$ form a clique → merge into a single new state (call it $D$)

Two cliques cover all 6 vertices → 2 states total.

Why this can collapse to 2 states even though outputs differ: the merge $\{D, G, H\}$ contains states with $z=1$ ($D, H$) and one with $z=0$ ($G$). That's fine in a Mealy FSM — the output is then a function of the merged state plus current input ($z$ depends on which "sub-row" you're acting like for that input). Within the merged row, each input column inherits the output from whichever original row stable-stated there. The stable-state outputs survive; the unstable-transition outputs become Mealy outputs.

Resulting 2-state Mealy table (Figure 9.46):

State$w_2w_1$=00=01=10=11$z$ on (00, 01, 10, 11)
A {ABC}AAAD000
D {DGH}DDAD101

The lesson: primitive flow tables look intimidatingly large, but the underlying state-transition graph is often almost trivial. Two-step reduction (partition + merger) extracts the minimum-state realization. Switching from Moore to Mealy framing during merger is a common trick — it relaxes the output-equality constraint and unlocks merges that would otherwise be blocked.

— example 9.10
9.26HardTier 2E?R
For a 4-state asynchronous FSM (Figure 9.55) whose transition diagram requires transitions between every pair of states, introduce three extra unstable states $E, F, G$ to enable a race-free 3-bit state assignment on a 3-cube. Modify the flow table to include the new states and derive the excitation table.
Context: Example 9.14 — adding extra unstable states to embed on a 3-cube

Figure 9.55a — original 4-state Moore flow table:

State$w_2 w_1$=00=01=10=11$z_2 z_1$
AAACB00
BABDB01
CCBCD10
DCADD11

The trouble: labeling the 8 stable cells 1–8 and tracing transitions reveals every pair of states has a direct transition — A↔B, A↔C, A↔D, B↔C, B↔D, C↔D. A 2-cube has only 4 vertices and 4 edges, so no 2-bit assignment can give all 6 pairs Hamming distance 1. 2-cube embedding is impossible.

The fix: move to a 3-cube. Three state bits give 8 vertices; we use 4 for the original states and 3 for new unstable intermediate vertices that break the impossible direct paths.

Step 1 — pick a base assignment: $A=000$, $B=001$, $C=100$, $D=010$. Direct cube-edge pairs (Hamming-1):

  • A↔B (000↔001) ✓ ; A↔C (000↔100) ✓ ; A↔D (000↔010) ✓
  • B↔D (001↔010) ✗ — distance 2; need intermediate
  • B↔C (001↔100) ✗ — distance 2; need intermediate
  • C↔D (100↔010) ✗ — distance 2; need intermediate

Step 2 — insert unstable vertices on each long path:

Long pathIntermediate vertexCodeSub-paths (each Hamming-1)
B ↔ DE011B(001)→E(011)→D(010)
B ↔ CF101B(001)→F(101)→C(100)
C ↔ DG110C(100)→G(110)→D(010)

The 8th vertex 111 stays unused.

Step 3 — modify the flow table. Whenever a transition would have crossed a long path, redirect it through the matching intermediate. For example, B→D on input $w_2w_1=10$ now becomes B→E (next-state E in row B); E is set up so that with input still 10, E→D (next-state D in row E). The table grows to 7 rows but the new entries are all "transit cells" that aren't stable for any input.

Step 4 — derive the excitation table. With 3 state variables $y_3 y_2 y_1$, write the next-state codes $Y_3 Y_2 Y_1$ for every (state, input) cell using the assignment above. The excitation entries can then be K-mapped to obtain the next-state logic, which drives the three feedback loops back to the state-bit latches/flip-flops.

What problem 9.26 asks specifically:

  1. Identify which of the 6 state-pairs need intermediates (the 3 long paths).
  2. Choose a 3-cube assignment that puts each state on a distinct vertex and provides single-bit-change paths between all required pairs (the assignment above is one valid solution).
  3. Insert E, F, G as unstable transit rows in the flow table.
  4. Build the excitation table (next-state binary codes) for the 7-row modified flow table.

Why this matters: race-free state assignments are mandatory in asynchronous design — if two state bits change simultaneously, the FSM may briefly visit an unintended cube vertex, which is itself a stable state in the wrong row, and the circuit can deadlock. By breaking every multi-bit transition into single-bit hops through transit states, only one bit ever changes at a time and races become impossible.

— example 9.14
9.31MediumTier 2E?R
Derive the flow table of an asynchronous circuit (Figure 9.76) by extracting next-state expressions $Y_1 = w_1\overline{w_2} + \overline{w_2}y_1 + w_1 y_1 \overline{y_2}$ and $Y_2 = w_2 + w_1 y_1 + w_1 y_2$, and output $z = y_2$. Construct the excitation table and resolve safe-race transitions in which both state variables change simultaneously.
Context: Example 9.19 — reverse-engineering a flow table from a circuit

The circuit (Figure 9.76) realizes an asynchronous FSM with state variables $y_1, y_2$, inputs $w_1, w_2$, output $z$. Logic:  $Y_1 = w_1\overline{w_2} + \overline{w_2}\,y_1 + w_1 y_1 \overline{y_2}$,  $Y_2 = w_2 + w_1 y_1 + w_1 y_2$,  $z = y_2$.

Figure 9.76 — asynchronous SOP circuit (Example 9.19) w1 w2 y1 y2 w̄2 ȳ2 A1 A2 A3 OR Y1 A4 A5 OR Y2 OR Y1 Δ y1 Δ y2 z Δ = gate delay (modeled per Figure 9.8); state variables y1, y2 fed back to AND-gate inputs.

Step 1 — build the excitation table. For each combination of $(y_2 y_1, w_2 w_1)$, evaluate the next-state codes $(Y_2 Y_1)$ and the output $z$:

$y_2 y_1$ \ $w_2 w_1$00011011$z$
00000110100
01010110110
10001010101
11111110111

Step 2 — identify stable states. A cell is stable iff $(Y_2 Y_1) = (y_2 y_1)$ for that input. Mark them (bold below in Figure 9.77's flow-table form). Each row corresponds to a present-state code.

Step 3 — name the states. Replace each binary code with a letter: $A = 00$, $B = 01$, $C = 10$, $D = 11$. Then:

State00011011$z$
A (00)ABCC0
B (01)BBCD0
C (10)ACCC1
D (11)DDCD1

Step 4 — check for safe-race transitions. A "race" occurs when both state variables change simultaneously in response to one input change. From the excitation table, identify cells where both $Y_2$ and $Y_1$ differ from the present $y_2$ and $y_1$. Examples:

  • $y_2 y_1 = 01, w_2 w_1 = 11$: next is $11$ — both bits change ($y_2: 0\to 1$, $y_1: 1\to 1$? actually only $y_2$ changes here, so single-bit). Inspect each entry carefully.
  • $y_2 y_1 = 11, w_2 w_1 = 10$: next is $10$ — only $y_1$ changes, single-bit. Safe.

Definition: safe race. A race is "safe" (non-critical) if the FSM eventually settles in the correct stable state regardless of which state variable changes first. A race is critical (unsafe) if intermediate states are stable for the same input — the circuit may get stuck. The textbook usually solves the analysis problem by tabulating each multi-bit transition and verifying that all single-bit-change paths converge to the same destination.

What problem 9.31 asks:

  1. Plug $w$ and $y$ values into $Y_1$ and $Y_2$ to fill the excitation table.
  2. Convert to a labeled flow table; identify stable cells.
  3. Check every multi-bit-change cell for race safety.
  4. Confirm output $z = y_2$ matches expected behavior in each row.
— example 9.19
9.3MediumTier 2?R
What is the difference between a stable state and an unstable state in an asynchronous circuit? Illustrate with a flow table example.
9.5MediumTier 2?R
Identify the static 1-hazard in the expression f = x₁x₂ + x̄₂x₃ when x₁=x₃=1 and x₂ changes from 1 to 0. How can it be eliminated?
9.8MediumTier 2?R
Show that a hazard-free SOP circuit for f(x₁,x₂,x₃) = Σm(1,2,3,5,7) requires an additional product term beyond the minimum SOP. Identify the required term using a K-map.
9.9MediumTier 2?R
Analyze an asynchronous circuit given by the equations Y₁ = x̄₁(x₂ + y₁) and Y₂ = x₁(x̄₂ + y₂). Derive the flow table and identify all stable states.
9.14HardTier 2E?R
Analyze a master-slave D flip-flop (two cascaded gated D latches) as an asynchronous sequential circuit. Derive the next-state expressions $Y_m = CD + \overline{C}y_m$ and $Y_s = Cy_m + \overline{C}y_s$, the four-state excitation table, and the corresponding flow table $S_1$ through $S_4$.
9.15HardTier 2E?R
Analyze the asynchronous circuit defined by $Y_1 = y_1 \overline{y_2} + w_1 \overline{y_2} + w_1 \overline{w_2} y_1$, $Y_2 = y_1 y_2 + w_1 y_2 + w_2 + \overline{w_1}\overline{w_2}\overline{y_1}$, and $z = y_1 \overline{y_2}$. Derive the excitation table, flow table, and a state diagram, and recognize the circuit as a simple two-coin vending machine controller.
9.17HardTier 2E?R
Design an asynchronous modulo-4 up-counter that counts pulses on input $w$. Use eight states (one for each edge of four pulses), choose a state assignment so that all transitions involve a single state-variable change, and derive next-state expressions $Y_1, Y_2, Y_3$ and output expressions $z_2, z_1$.
9.19HardTier 2E?R
Reduce the primitive flow table for a candy-vending machine that accepts nickels and dimes and dispenses when 10 cents is reached (Figure 9.26b). Apply the partitioning procedure first, then merge compatible rows to obtain the optimized 4-state flow table.
Context: Figure 9.26b — primitive flow table for the vending FSM

Spec. Asynchronous FSM with two inputs $D$ (dime sensed) and $N$ (nickel sensed). Output $z=1$ when at least 10 ¢ has been collected (dispense). 15 ¢ overpay gives no change. Asynchronous-design rule: only one input variable may change at a time, so $DN=11$ is unreachable.

Six-state initial state diagram (Moore-type, Figure 9.26a):

  • A ($z=0$) — reset, 0 ¢. $N=1$→B; $D=1$→C
  • B ($z=0$) — 5 ¢, sensor still showing nickel. When $N$ clears → D
  • C ($z=1$) — 10 ¢ via dime, sensor still showing dime. When $D$ clears → A
  • D ($z=0$) — 5 ¢, sensor idle. $N=1$→E; $D=1$→F
  • E ($z=1$) — 10 ¢ via 5+5. When sensor clears → A
  • F ($z=1$) — 15 ¢ via 5+10. When sensor clears → A

Primitive flow table (Figure 9.26b) — one stable state per row (bold = stable); dashes are don't-cares (forbidden $DN=11$ and impossible-transition entries):

State$DN$=00=01=10=11$z$
AABC0
BDB0
CAC1
DDEF0
EAE1
FAF1

What the problem asks (two-step reduction):

  1. Partitioning: group by output and refine. The output partition is $\{A, B, D\}$ ($z=0$) and $\{C, E, F\}$ ($z=1$). Refining by next-state behavior across columns produces the equivalence pair $E \equiv C$ (both stable on $DN=01$/$10$ respectively but with the same "go to A on 00" pattern) and other compatible-state findings.
  2. Row merging: combine rows whose specified next-state entries don't conflict (don't-cares can be filled either way). After merging, the table collapses from 6 rows to 4.

Result (Figure 9.27 in the textbook). The 4 surviving states correspond to {idle, 5 ¢ collected with sensor cleared, 5 ¢ with sensor active, ≥10 ¢ collected}. Stable-state pairs that originally distinguished "10 ¢ via single dime" vs "10 ¢ via 5+5" merge because the asynchronous output and stable-state behavior are identical from that point on.

Why primitive tables are reducible: the one-stable-per-row format is verbose by construction. Many of those rows turn out to be doing the same thing once you allow don't-cares to be filled in. The two-step partition-then-merge procedure is the canonical asynchronous-FSM reduction algorithm.

— example 9.7
9.21HardTier 2E?R
Reduce the 8-row flow table in Figure 9.38 first by partitioning, then by merging using both Moore-style and Mealy-style merger diagrams. Compare the resulting state counts and discuss when the Mealy form yields fewer states.— example 9.9
9.23MediumTier 2E?R
For the parity-generator FSM with states $A,B,C,D$, draw a transition diagram on a 2-cube for the state assignment $A=00, B=01, C=10, D=11$ and show that it requires diagonal transitions. Then verify that the alternative assignment $A=00, B=01, C=11, D=10$ eliminates all diagonal paths.
9.24HardTier 2E?R
For the simple two-device arbiter FSM, show that no 3-state, 2-state-variable assignment yields a Hamming-distance-1 transition graph. Add a fourth (unstable) state $D$ to break the diagonal transition between $B$ and $C$, modify the flow table accordingly, and ensure that the unstable state produces a safe output value.
9.25HardTier 2E?R
A 4-state flow table (Figure 9.52a) has 7 stable-state entries. Relabel the table to enumerate stable-state instances, draw a transition diagram, and exploit an unspecified entry to find a state assignment that maps onto a 2-cube without diagonal transitions. Specify any required Mealy-style outputs to avoid output glitches in unstable states.
Context: Example 9.13 — exploiting an unspecified entry to get a race-free state assignment

Figure 9.52a — original 4-state Moore flow table (bold = stable, "—" = unspecified):

State$w_2 w_1$=00=01=10=11$z_2 z_1$
AABCA00
BBBDC01
CACDC10
DBDA11

Counting stable-state cells: A×2, B×2, C×2, D×1 → 7 stable instances.

Figure 9.52b — relabeled with stable-instance numbers 1–7 (each stable cell gets a unique label so we can name transitions by their destination):

State00011011
A1472
B3476
C1576
D372

Why the relabeling helps: a transition like "C → A" in column 00 ends at the stable cell labeled 1 — so we annotate that arrow with "1". Multiple transitions ending at the same stable instance can share a label.

Step 1 — first transition diagram (assignment A=00, B=01, C=11, D=10). Connect every pair of states that exchange transitions; the offending arrows are diagonals on the 2-cube (Hamming distance 2):

  • A↔C diagonal carries labels 1 (C→A) and 7 (A→C)
  • B↔D diagonal carries labels 3 (D→B) and 7 (B→D)

Label-7 paths (transitions to stable D) have alternative routes via other states — they can be re-routed off the diagonal. But labels 1 and 3 are stuck on diagonals — no alternate path. So this assignment fails.

Step 2 — try swapping B and C codes (A=00, B=11, C=01, D=10). Now A↔B is the diagonal and B↔D becomes adjacent. Recheck:

  • C→A: 01 → 00, Hamming-1 ✓
  • D→B: 10 → 11, Hamming-1 ✓
  • A→B (label 4): 00 → 11, Hamming-2 ✗ — still diagonal

Step 3 — exploit the unspecified entry. Row D, column 01 is "—". Fill it with $B$ (so D becomes a "pass-through" for the 01-input). Now the transition $A \to B$ on input 01 can be re-routed as $A \to D \to B$ (two single-bit hops: 00→10→11). The diagonal A↔B disappears from the transition graph because nobody needs it any more.

Augmented transition diagram (Figure 9.53c):

D 10 B 11 A 00 C 01 3, 7, 4 6, 7 1, 7 2, 7, 4 All edges are Hamming-distance 1 — no diagonals

All edges are single-bit changes. The 2-cube embedding works → state assignment A=00, B=11, C=01, D=10 is race-free.

Why a Mealy model is needed afterward. Several transitions now route through unstable intermediate states (e.g., A→D→B). If the output were strictly $f(\text{state})$ (Moore), the FSM would briefly show D's output (11) while passing through it on the way to B (whose output is 01). That's an output glitch. To suppress glitches, the modified flow table (Figure 9.54a) re-specifies the output column-by-column as a function of $(\text{state}, w)$: in unstable cells, the output is forced to match the eventual stable destination's output, not the unstable transition state's output.

The general technique:

  1. Number stable instances → cleaner transition labeling.
  2. Draw transition graph; identify offending diagonals.
  3. Re-route diagonal transitions through alternative states whenever a label has multiple paths available.
  4. Use unspecified entries to add compatible alternative paths (this is the key insight — don't-cares aren't just for next-state simplification, they create new transition paths too).
  5. Switch to Mealy outputs to suppress glitches in the now-extended transition routes.
— example 9.13
9.27HardTier 2E?R
Re-implement the FSM of Example 9.14 by replacing each of its 4 states with an equivalent pair of states, so that the 8 vertices of a 3-cube are used. Verify that the resulting transition diagram has no diagonal paths and modify the flow table accordingly.
Context: Example 9.14 — state-splitting approach (alternative to inserting unstable transit states)

Same FSM as in problem 9.26 (Figure 9.55), where the 4-state transition diagram has all 6 state-pairs requiring transitions and can't embed on a 2-cube.

Figure 9.55a — flow table (stable states underlined; output $z_2 z_1$):

state$w_2w_1{=}00$$01$$10$$11$$z_2z_1$
AAACB00
BABDB01
CCBCD10
DCADD11
Figure 9.56a — transition diagram (K4) A B C D diagonal (Hamming-2 — blocks 2-cube embedding)

Every pair of states has at least one transition (the diagram is $K_4$), so any 2-bit assignment forces at least one Hamming-2 step — that's the diagonal edge. Adding a third state-bit gives a 3-cube with 8 vertices, and the trick is to use those extra vertices to break the diagonals into single-bit hops.

Problem 9.26 solves it by inserting 3 extra unstable states (E, F, G). This problem solves it differently: replicate each of the 4 states as an equivalent pair, giving 8 states total — exactly enough to fill the 8 vertices of a 3-cube.

The state-splitting recipe:

  1. For each original state $X$, introduce a clone $X'$ with the same outputs and the same stable-cell set. Both $X$ and $X'$ are valid stable states.
  2. Each transition that originally entered $X$ may instead enter $X'$, depending on which choice gives a single-bit code change.
  3. Pick a 3-bit assignment for the 8 states such that every required (state, target) edge is on a cube edge (Hamming-1).

Sample assignment that works: $A=000$, $A'=001$, $B=011$, $B'=010$, $C=110$, $C'=111$, $D=101$, $D'=100$. Walk the cube vertices in Gray-code order — each consecutive pair differs by one bit, so every "long" diagonal in the original 4-state graph can be replaced by routing to the appropriate clone of the destination.

Concrete example: A→B normally requires a 2-bit jump. Instead, route A=000 → A'=001 (1-bit) → B=011 (1-bit) → B'=010 (1-bit). The transit goes through a clone (A') and lands in the right state's clone (B'). Outputs match, so the user never knows which clone they're in.

Trade-off vs. the unstable-state approach (problem 9.26):

ApproachTotal statesStable rowsExcitation logic
Insert E, F, G as transit (9.26)74 (original)3 transit cells per state — moderate complexity
Split each state into pair (9.27)88 (each original split)Cleaner symmetry; uses every cube vertex

What 9.27 specifically asks:

  1. Pair each of A, B, C, D with a clone $A', B', C', D'$.
  2. Assign 3-bit codes so every transition is Hamming-1.
  3. Modify the flow table: replace 4 rows with 8 rows; specify which clone the transitions enter.
  4. Verify the new transition diagram has no diagonal paths.

When to choose which approach: state-splitting tends to give simpler next-state logic (the symmetry helps K-map minimization), but doubles the row count and uses all cube vertices. Insertion of unstable transit states (9.26) has fewer rows but the transit cells are explicit "non-stable" places that must be carefully verified to never permanently latch.

— example 9.14
9.28HardTier 2E?R
Examine the minimum-cost two-level realization of the master-slave D flip-flop derived from $Y_m = CD + \overline{C}y_m$ and $Y_s = Cy_m + \overline{C}y_s$. Identify the static hazard that causes the circuit to settle into an incorrect stable state when $C$ falls from 1 to 0, and add the redundant prime implicants $Dy_m$ and $y_m y_s$ to remove it.
9.29MediumTier 2E?R
Show that for a SOP circuit with don't-care minterms, only product terms covering pairs of adjacent 1s are needed for hazard freedom—not all prime implicants. Apply this to the function in Figure 9.64 to derive a hazard-free realization $f = x_1\overline{x_3} + \overline{x_2}\overline{x_3} + x_3 x_4$.— example 9.17
9.30MediumTier 2E?R
Analyze the static hazard in a POS circuit (Figure 9.65a). When $x_1=x_3=0$ and $x_2$ rises from 0 to 1, identify the unequal-delay path that produces a $0\to 1\to 0$ glitch on the output. Add the sum term that covers all adjacent 0s to obtain a hazard-free POS realization.
Context: Example 9.18 — static hazard in a POS circuit

Figure 9.65a — the POS circuit: $f = (x_1 + x_2)(\overline{x_2} + x_3)$ realized as two OR gates feeding an AND gate. Internal nodes $p = x_1 + x_2$ and $q = \overline{x_2} + x_3$.

The hazard scenario. Set $x_1 = x_3 = 0$ and toggle $x_2$ from 0 to 1. The function should stay at $f = 0$ throughout (both inputs to the AND cannot simultaneously be 1 in steady state):

$x_2$$p = x_1 + x_2$$q = \overline{x_2} + x_3$$f = p \cdot q$
0 (steady)0+0 = 01+0 = 10·1 = 0 ✓
1 (steady)0+1 = 10+0 = 01·0 = 0 ✓

The glitch. During the $x_2: 0 \to 1$ transition, $p$ rises from 0 to 1 (the OR sees $x_2$ go up) before $q$ falls from 1 to 0 (because the inverter on $\overline{x_2}$ adds an extra delay before the second OR sees the change). For a brief window $p = q = 1$, so $f = 1$. The output exhibits a $0 \to 1 \to 0$ glitch — a static-0 hazard.

Why POS circuits hazard on adjacent 0s. In a POS circuit, the AND of OR-terms produces 0 only when at least one OR-term is 0. A hazard occurs at the boundary between two K-map 0-cells where no single sum-term covers both — momentarily both terms can be 1, giving $f = 1$.

The fix. Add a redundant sum-term $(x_1 + x_3)$ that covers both adjacent 0-cells (it is 0 only when $x_1 = x_3 = 0$). With this extra term, every transition between adjacent 0s leaves at least one OR-term at 0 throughout the transition:

$$f_{\text{hazard-free}} = (x_1 + x_2)(\overline{x_2} + x_3)(x_1 + x_3)$$

Cost of removing the hazard: one extra OR2 gate plus one input to the AND. The extra gate is logically redundant — it does not change the function — but it bridges the gap that allowed the glitch.

Dual rule (memorize):

  • SOP circuits: hazards on transitions between adjacent 1-cells. Fix: add product term covering each pair of adjacent 1s.
  • POS circuits: hazards on transitions between adjacent 0-cells. Fix: add sum term covering each pair of adjacent 0s.
— example 9.18
9.32MediumTier 2E?R
Examine the next-state expressions derived in Example 9.19 for hazards. Use Karnaugh maps for $Y_1$ and $Y_2$ to identify any prime implicant that, if missing, leaves a static hazard. Add the missing implicant to obtain a hazard-free realization.— example 9.19
9.33HardTier 2E?R
Design an asynchronous circuit with input $w$ and output $z$ that replicates every second pulse on $w$ as a pulse on $z$. Provide a state diagram, flow table, race-free state assignment, and final next-state and output expressions.
9.34HardTier 2E?R
Reduce the 8-row flow table of Figure 9.81 using the partitioning procedure and a merger diagram (preserving the Moore model). Then find a state assignment that allows mapping onto a 3-cube without diagonal transitions and derive the excitation table.
Context: Example 9.22 — full reduction + state assignment for an 8-row Moore flow table

Figure 9.81 — original 8-row primitive flow table (Moore-type, output $z$ depends only on state):

State$w_2 w_1$=00=01=10=11$z$
AAEC0
BEHB1
CGCF0
DADB1
EGEB0
FDCF0
GGEC0
HAHB1

Stage 1 — Partitioning by output groups (refine until stable):

$$P_1 = (ACEFG)(BDH) \qquad P_2 = (AG)(B)(C)(D)(E)(F)(H) \qquad P_3 = P_2$$

Equivalence found: $A \equiv G$. Merge them into a single state (call it $A$). Result: 7-row table (Figure 9.82).

Stage 2 — Merger diagram on the 7-row reduced table identifies these compatible-pair merges:

  • $A$ and $E$ — same don't-care pattern, compatible next-states
  • $C$ and $F$ — compatible next-states
  • $D$ and $H$ — compatible next-states (both produce $z=1$, both go to $B$ on input 11)

After merging: 4-state table (Figure 9.84). Relabel for state assignment.

Stage 3 — State assignment. The relabeled 4-state transition diagram (Figure 9.86a) has one diagonal: D→A on some input, labeled "1" — Hamming-2 jump.

The fix: exploit a don't-care entry to route the diagonal D→A through state C (Hamming-1 hops): $D \to C \to A$. After this re-routing (Figure 9.86b), the transition diagram has no diagonals and embeds onto a 2-cube. State assignment becomes simply $A=00, B=01, C=11, D=10$ (or similar Gray-code mapping).

Stage 4 — Excitation table. With the assignment fixed, write next-state codes $(Y_2 Y_1)$ for every (state, input) cell. K-map the columns to derive logic for $Y_1$ and $Y_2$. Output $z$ is a function of state alone (Moore), so it K-maps directly from the present-state bits.

The full pipeline summary:

StageOperationRows after
0Original primitive flow table8
1Partitioning ($A \equiv G$)7
2Merger diagram (A+E, C+F, D+H)4
3State assignment + diagonal-routing fix4 (no change in count)
4Excitation table → K-maps → next-state logic

What problem 9.34 specifically asks: walk through stages 1–4 above, preserving the Moore model throughout (so the merger constraint is "same output in stable cells", not the looser Mealy compatibility).

— example 9.22
9.36HardTier 2?R
Synthesize an asynchronous circuit for a set-reset latch with inputs S and R: when S=1 output goes to 1, when R=1 output goes to 0, S=R=1 is not allowed. Derive the primitive flow table, merge rows, assign states, and derive output equations.
9.37MediumTier 2?R
Perform state reduction on the following flow table: States A–D, Inputs x₁x₂={00,01,10,11}. Identify equivalent states and produce the reduced table.
9.38MediumTier 2?R
Use one-hot state encoding to implement a 3-state asynchronous FSM. What are the advantages over binary encoding for asynchronous circuits?
9.39EasyTier 2?R
Why are asynchronous circuits more difficult to design than synchronous circuits? List at least three specific challenges.
9.40MediumTier 2?R
Explain the difference between the primitive flow table and the merged (reduced) flow table. Why is merging necessary before state assignment?
9.41MediumTier 2?R
A dynamic hazard occurs in the circuit output sequence 1→0→1→0 when the intended transition is 1→0. Under what conditions do dynamic hazards occur? How can they be eliminated?
9.42EasyTier 2?R
What is a "don't happen" input combination in asynchronous design? How are they used in the design process?
9.43HardTier 2?R
Design an asynchronous circuit that acts as an arbiter for two request signals r₁ and r₂. The circuit should grant access (g₁ or g₂) to the first requester and hold until that request is released.

Tier 3 · Residual

9.44HardTier 3?R
Find a race-free state assignment for a 4-state asynchronous circuit using transition diagrams. Verify that no critical races exist.
9.45HardTier 3?R
Design an asynchronous vending machine controller: it accepts 5¢ and 10¢ coins. When the total reaches 15¢ or more, it dispenses a product and resets. Derive the complete circuit starting from the primitive flow table.
9.46HardTier 3?R
Show how to use additional state variables to achieve a race-free state assignment for a 5-state asynchronous circuit. Explain the shared-row technique.
9.47HardTier 3?R
Given a flow table with 6 rows and inputs x₁, x₂, use the merger diagram to determine the maximum number of compatible groups. Perform the state assignment and derive the next-state equations.
9.48HardTier 3?R
Prove that any function implemented in a two-level SOP form will have no static 0-hazards. When can static 0-hazards appear?