Additional problems organized by chapter, then by tier.
assign statement. Write a simple testbench that applies all 16 input combinations.+ operator and outputs a 9-bit result (including carry-out).generate statements to create the partial product and addition logic. Verify with a testbench.? :, write a one-line assign statement that implements a 4-to-1 multiplexer.<, ==, >.function that takes a 4-bit BCD input and returns the corresponding 7-segment display output (7 bits).for loop in Verilog to describe an 8-bit population count circuit (counts the number of 1s in an 8-bit input).casex and casez in Verilog. When would you use each?task that swaps two 8-bit values. Call this task from a module to sort three inputs in ascending order.generate construct. Verify for n = 3.Load=1, the counter loads a 4-bit value D; otherwise it counts up. Include an asynchronous reset. Write the Verilog code.1000?0000? How many unique states does it pass through?always @(posedge Clock or negedge Resetn).Sin and parallel outputs Q[3:0], write a Verilog module that detects when the serial pattern 1011 has been completely shifted in.001, trace all states in the sequence. Is this a maximal-length sequence?1001 or 1111 patterns on input w (overlapping allowed). Verify with the sequence w: 010111100110011111.D₁ = x ⊕ Q₂ and D₂ = Q₁.(* synthesis, encoding = "one-hot" *)) affects the synthesized hardware. Compare binary, Gray, and one-hot for an 8-state FSM.w₁ and w₂. It outputs z=1 when w₁=w₂ for four consecutive clock cycles. Derive the state diagram and Verilog code.110 or 101 patterns are detected (overlapping). Derive the minimal state table, state assignment, and complete implementation.assign bus = enable ? data : 8'bz;) to connect two modules to a shared 8-bit bus.Figure 8.14a is a chain of four 2-input NAND gates. Each gate output gets a fresh inversion bubble, so analysis is easier if we push bubbles around using DeMorgan: $\overline{AB} = \overline{A} + \overline{B}$.
Direct trace (NAND outputs). Each $P_i$ is the NAND of its two inputs:
$P_1 = \overline{x_1 x_2}, \quad P_2 = \overline{P_1 \cdot x_3}, \quad P_3 = \overline{P_2 \cdot x_4}, \quad f = \overline{P_3 \cdot x_5}.$
Bubble-push from the output. Apply DeMorgan to $f$, then unwind:
$f = \overline{P_3 \cdot x_5} = \overline{P_3} + \overline{x_5} = (P_2 \cdot x_4) + \overline{x_5}.$
$P_2 \cdot x_4 = \overline{P_1 \cdot x_3}\cdot x_4 = (\overline{P_1} + \overline{x_3})\,x_4 = (x_1 x_2 + \overline{x_3})\,x_4.$
Therefore $f = (x_1 x_2 + \overline{x_3})\,x_4 + \overline{x_5} = x_1 x_2 x_4 + \overline{x_3}\, x_4 + \overline{x_5}.$
Why this works (the bubble-pushing rule). A NAND can always be redrawn as an OR with both inputs inverted: $\overline{AB} = \overline{A} + \overline{B}$. Cascaded NANDs alternately propagate AND/OR layers, with bubbles cancelling on internal wires when they meet (two bubbles on the same wire ≡ no bubble). After cancellation, surviving bubbles end up only on the primary inputs that lit up the inversions — here, $x_3$ and $x_5$ — yielding the AND-OR equivalent in Figure 8.14c.
Counting the survivors. Travel from $f$ back to each input. Count NAND-output bubbles on the path: an even count cancels, an odd count leaves the input complemented. For $x_1, x_2$: two bubbles (at NAND1 and NAND4) — wait, NAND1 output bubble is on the output side, then it enters NAND2 which has no input bubble; bubbles only appear at NAND outputs, and every NAND output is consumed by the next NAND. So pair-cancellation between NAND1 output bubble and the implicit DeMorgan-redrawn NAND2 (= AND with input bubbles) yields a clean AND. Trace each input: $x_1, x_2, x_4$ → no surviving bubble; $x_3, x_5$ → one surviving bubble each (complemented). Matches the algebraic result above.
f = ac + ad + bc + bd + e using only NAND gates.f = abd + abe + acd + ace. Show the factored form.f = s·d₁ + s̄·d₀ with ordering s < d₀ < d₁. Then try ordering d₀ < d₁ < s. Compare sizes.f(x₁,...,x₄) = Σm(0,3,4,7,9,10,13,14) assuming gates have a maximum fan-in of 2.The K-map of $f(x_1,x_2,x_3,x_4,x_5)$ — two 4×4 panels (one per value of $x_5$); columns indexed by $x_1 x_2$, rows by $x_3 x_4$:
| $x_5 = 0$ | ||||
|---|---|---|---|---|
| $x_3 x_4$ \ $x_1 x_2$ | 00 | 01 | 11 | 10 |
| 00 | 1 | 0 | 0 | 0 |
| 01 ← | 0 | 1 | 1 | 1 |
| 11 | 1 | 0 | 0 | 0 |
| 10 ← | 0 | 1 | 1 | 1 |
| $x_5 = 1$ | ||||
|---|---|---|---|---|
| $x_3 x_4$ \ $x_1 x_2$ | 00 | 01 | 11 | 10 |
| 00 | 0 | 0 | 0 | 0 |
| 01 ← | 1 | 1 | 1 | 1 |
| 11 | 0 | 0 | 0 | 0 |
| 10 ← | 1 | 1 | 1 | 1 |
Step 1 — observe row patterns. Each row depends only on $(x_1, x_2, x_5)$. Two distinct patterns appear:
Step 2 — identify which rows have which pattern. The "←" rows ($x_3 x_4 = 01, 10$) are exactly the cases where $x_3 \ne x_4$. So let $k(x_3, x_4) = x_3 \oplus x_4$.
Then: $k=1$ rows (01, 10) → $f = g$; $k=0$ rows (00, 11) → $f = \overline{g}$.
Step 3 — combine.
$$f = k\cdot g + \overline{k}\cdot \overline{g} = \overline{g \oplus k} = g \odot k$$So $h(g, k) = g \odot k$ (XNOR).
Decomposed circuit:
Cost comparison:
| Realization | Gates | Total inputs | Cost |
|---|---|---|---|
| Multilevel: $f = g \odot k$, $g = x_1+x_2+x_5$, $k = x_3 \oplus x_4$ | 3 (OR3, XOR2, XNOR2) | 3+2+2 = 7 | 10 |
| Direct minimum-cost SOP (~16 ones, no large rectangles) | ~7–10 ANDs + 1 OR | ~25–30 | ~35+ |
The decomposition pays off because the two K-map row patterns depend on disjoint variable sets. The textbook lesson: spatial regularity in the K-map (rows or columns repeating) signals an opportunity to factor out a subfunction.
The trick. Add two inverters (a "bubble pair") on a wire — logically they cancel, so the circuit's function is unchanged. Then absorb each bubble into the gate at one end of the wire, converting AND/OR gates into NAND/NOR gates by DeMorgan's theorem.
DeMorgan equivalences (the engine):
$$\overline{a \cdot b} = \overline{a} + \overline{b} \qquad \overline{a + b} = \overline{a} \cdot \overline{b}$$Reading this as gate symbols:
| Original gate | = equivalent | Use to build |
|---|---|---|
| AND with output bubble | NAND | NAND-only |
| OR with input bubbles | NAND (by DeMorgan) | NAND-only |
| OR with output bubble | NOR | NOR-only |
| AND with input bubbles | NOR (by DeMorgan) | NOR-only |
The conversion recipe. Walk every wire in the circuit and add a bubble-pair so that each gate has the bubble pattern it needs:
What's left over: primary inputs and the final output may have an unmatched bubble that doesn't pair up with another gate's bubble. Each leftover bubble is implemented as a separate inverter — which can be a NAND (or NOR) with its inputs tied together:
$$\text{NAND}(x, x) = \overline{x \cdot x} = \overline{x} \qquad \text{NOR}(x, x) = \overline{x + x} = \overline{x}$$So the final circuit is uniformly NAND (or NOR) gates, no other gate types needed.
Step-by-step on the textbook's 4-level circuit:
For NOR-only conversion (Figure 8.11), swap the rules: ORs get output bubbles, ANDs get input bubbles. Leftover bubbles at $x_2, x_3, x_4$ become NOR-as-inverter cells (Figure 8.11b).
Tiny illustration of the bubble cancellation:
The two bubbles on the middle wire cancel; the AND with output-bubble is a NAND; the OR with input-bubbles is also a NAND (by DeMorgan). Same function, all-NAND realization.
The strategy: label every internal wire with a name ($P_1, P_2, \ldots$), write the function at each gate output, then substitute back to get $f$ in terms of the primary inputs.
Figure 8.12 — the circuit (4 levels deep, AND/OR alternation, inputs $x_1$–$x_7$):
Trace from inputs forward: $P_1 = x_2 x_3$, $P_2 = x_5 + x_6$, $P_3 = x_1 + P_1 = x_1 + x_2 x_3$, $P_4 = x_4 P_2 = x_4(x_5+x_6)$, $P_5 = P_4 + x_7 = x_4(x_5+x_6) + x_7$, giving $f = P_3 \cdot P_5 = (x_1 + x_2 x_3)\bigl(x_4(x_5+x_6) + x_7\bigr)$.
Two-level SOP form (distributive law): $f = x_1 x_4 x_5 + x_1 x_4 x_6 + x_1 x_7 + x_2 x_3 x_4 x_5 + x_2 x_3 x_4 x_6 + x_2 x_3 x_7$.
6 product terms, total 25 input literals (3+3+2+4+4+3) plus the 6-input OR.
Cost comparison:
| Form | Gates | Total inputs | Cost | Delay |
|---|---|---|---|---|
| Multilevel (Figure 8.12) | 6 (P₁,P₂ + P₃,P₄ + P₅ + f) | 2+2+2+2+2+2 = 12 | 18 | 4 gate-delays |
| Two-level SOP | 7 (six ANDs + one OR) | 3+3+2+4+4+3 + 6 = 25 | 32 | 2 gate-delays |
Trade-off: the multilevel form has lower gate cost but more depth (slower); the two-level form is faster but more expensive. Multilevel optimization is mostly an area-vs-speed knob.
The function:
$$f(x_1,x_2,x_3,x_4) = \sum m(0,1,3,4,7,11,13,15) + D(9,12,14)$$K-map (4-variable, columns $x_3 x_4$, rows $x_1 x_2$, $d$ = don't-care):
| $x_1 x_2$ \ $x_3 x_4$ | 00 | 01 | 11 | 10 |
|---|---|---|---|---|
| 00 | 1 (m₀) | 1 (m₁) | 1 (m₃) | 0 |
| 01 | 1 (m₄) | 0 | 1 (m₇) | 0 |
| 11 | $d$ (m₁₂) | 1 (m₁₃) | 1 (m₁₅) | $d$ (m₁₄) |
| 10 | 0 | $d$ (m₉) | 1 (m₁₁) | 0 |
Example 8.23 uses the Quine–McCluskey tabular method to derive a minimum-cost SOP. The selected cover is $C = \{0x00,\ x0x1,\ xx11,\ 1xx1\}$, giving
$$f_\text{SOP} = \overline{x_1}\,\overline{x_3}\,\overline{x_4} + \overline{x_2}\,x_4 + x_3\,x_4 + x_1\,x_4$$Example 8.24 uses the *-product operation on the same function and derives the full set of prime implicants $P = \{x_1\overline{x_3}\overline{x_4},\ \overline{x_3}\overline{x_4},\ \overline{x_1}\overline{x_2}\overline{x_3},\ \overline{x_2}x_3\overline{x_4},\ \overline{x_2}x_4,\ x_1 x_4,\ x_1 x_2\}$ — confirming the same minimum cover from a different algorithm.
What problem 8.37 asks: compute three realizations of this same function and compare costs.
(a) Minimum-cost SOP (from Example 8.23):
$$f = \overline{x_1}\,\overline{x_3}\,\overline{x_4} + \overline{x_2}\,x_4 + x_3\,x_4 + x_1\,x_4$$Gates: 4 ANDs (3-input × 1, 2-input × 3) + 1 OR (4-input). Inputs: $3+2+2+2 = 9$ (AND) + 4 (OR) = 13. Cost = 5 gates + 13 inputs = 18.
(b) Minimum-cost POS — derive from the off-set ($f=0$ at minterms 2, 5, 6, 8, 10; with D=9,12,14 used to enlarge product groups). K-map grouping of zeros yields the maxterm cover, e.g.
$$f_\text{POS} = (x_2 + x_3 + x_4)\,(\overline{x_1} + x_4)\,(\overline{x_2} + x_4 + \overline{x_3})$$(Exact cover depends on don't-care assignment; this is one valid minimum cover.) Gates: 3 ORs (3-input × 3) + 1 AND (3-input). Inputs: $3+3+3 = 9$ (OR) + 3 (AND) = 12. Cost = 4 gates + 12 inputs = 16.
(c) Multilevel factored realization — start from the SOP and factor out the common literal $x_4$:
$$f = \overline{x_1}\,\overline{x_3}\,\overline{x_4} + x_4\,(\overline{x_2} + x_3 + x_1)$$Gates: 1 AND3 ($\overline{x_1}\overline{x_3}\overline{x_4}$), 1 OR3 ($\overline{x_2}+x_3+x_1$), 1 AND2 ($x_4 \cdot $ above OR), 1 OR2 (final). Inputs: $3 + 3 + 2 + 2 = 10$. Cost = 4 gates + 10 inputs = 14.
Comparison:
| Form | Gates | Inputs | Cost | Delay |
|---|---|---|---|---|
| (a) Min SOP | 5 | 13 | 18 | 2 (AND→OR) |
| (b) Min POS | 4 | 12 | 16 | 2 (OR→AND) |
| (c) Multilevel factored | 4 | 10 | 14 | 3 (OR→AND→OR) |
Trade-off: SOP and POS are two-level — fastest at 2 gate-delays — but pay in gate count. Multilevel factored cuts cost by ~22% but adds one extra gate-delay because the signal traverses an extra logic level. Whether the multilevel form wins depends on the technology timing budget: in slow-clock FPGA fabric, area savings dominate; in critical-path ASIC datapaths, the two-level form's depth advantage may matter more.
f = Σm(0,2,3,5,7,8,10,11,14,15,24,26,27,29,31). Find all prime implicants and a minimum cover.f = x̄₁x₂ + x₁x̄₃ as a set of cubes.f = x₃x₅ + x₁x₂x₄ + x̄₁x₂x̄₄ + x₁x̄₃x₄ + x₁x₃x̄₄ + x₁x̄₂x₅ + x̄₁x₂x₅, derive a minimum-cost multilevel circuit.f(x₁,...,x₄) = Σm(4,7,8,11) + D(12,15). Compare costs.f = x₁x₂ + x₃x₄ + x₅x₆, which ordering would you expect to produce a smaller BDD: interleaved (x₁f(x₁,...,x₄) = Σm(0,4,8,13,14,15) assuming inputs are available in uncomplemented form only. Use functional decomposition.f = ab + cd to minimize total cost.t₁ = a + b, t₂ = c·d, t₃ = t₁·e, f = t₂ + t₃. Derive the flattened SOP expression, then re-factor for minimum cost with a fan-in constraint of 2.Setup. Figure 9.43 is an 8-row primitive flow table for an asynchronous Moore-like FSM. Inputs $w_2 w_1$, rows $A$–$H$, output $z$ varies per row. The dramatic claim: this 8-row table reduces all the way down to just 2 states via partitioning + merger, but the result is a Mealy FSM (some output depends on input not just state).
Stage 1 — Partitioning. Group by output and refine by next-state successors:
$$P_1 = (AF)(BEG)(C)(D)(H) \qquad P_2 = (AF)(BE)(G)(C)(D)(H) \qquad P_3 = P_2$$So the partitioning step proves $A \equiv F$ and $B \equiv E$. Replace $F$ with $A$ and $E$ with $B$ → 6-row table (Figure 9.44 in the textbook):
| State | $w_2w_1$=00 | =01 | =10 | =11 | $z$ |
|---|---|---|---|---|---|
| A | A | B | C | — | 0 |
| B | A | B | — | H | 0 |
| C | A | — | C | H | 0 |
| D | D | G | C | — | 1 |
| G | D | G | — | H | 0 |
| H | — | G | C | H | 1 |
Stage 2 — Merger diagram. Build a graph where each row is a vertex and each compatible pair (no conflicting next-state entries; Mealy-output compatibility) is an edge. From Figure 9.45:
Two cliques cover all 6 vertices → 2 states total.
Why this can collapse to 2 states even though outputs differ: the merge $\{D, G, H\}$ contains states with $z=1$ ($D, H$) and one with $z=0$ ($G$). That's fine in a Mealy FSM — the output is then a function of the merged state plus current input ($z$ depends on which "sub-row" you're acting like for that input). Within the merged row, each input column inherits the output from whichever original row stable-stated there. The stable-state outputs survive; the unstable-transition outputs become Mealy outputs.
Resulting 2-state Mealy table (Figure 9.46):
| State | $w_2w_1$=00 | =01 | =10 | =11 | $z$ on (00, 01, 10, 11) | |||
|---|---|---|---|---|---|---|---|---|
| A {ABC} | A | A | A | D | 0 | 0 | 0 | — |
| D {DGH} | D | D | A | D | 1 | 0 | — | 1 |
The lesson: primitive flow tables look intimidatingly large, but the underlying state-transition graph is often almost trivial. Two-step reduction (partition + merger) extracts the minimum-state realization. Switching from Moore to Mealy framing during merger is a common trick — it relaxes the output-equality constraint and unlocks merges that would otherwise be blocked.
Figure 9.55a — original 4-state Moore flow table:
| State | $w_2 w_1$=00 | =01 | =10 | =11 | $z_2 z_1$ |
|---|---|---|---|---|---|
| A | A | A | C | B | 00 |
| B | A | B | D | B | 01 |
| C | C | B | C | D | 10 |
| D | C | A | D | D | 11 |
The trouble: labeling the 8 stable cells 1–8 and tracing transitions reveals every pair of states has a direct transition — A↔B, A↔C, A↔D, B↔C, B↔D, C↔D. A 2-cube has only 4 vertices and 4 edges, so no 2-bit assignment can give all 6 pairs Hamming distance 1. 2-cube embedding is impossible.
The fix: move to a 3-cube. Three state bits give 8 vertices; we use 4 for the original states and 3 for new unstable intermediate vertices that break the impossible direct paths.
Step 1 — pick a base assignment: $A=000$, $B=001$, $C=100$, $D=010$. Direct cube-edge pairs (Hamming-1):
Step 2 — insert unstable vertices on each long path:
| Long path | Intermediate vertex | Code | Sub-paths (each Hamming-1) |
|---|---|---|---|
| B ↔ D | E | 011 | B(001)→E(011)→D(010) |
| B ↔ C | F | 101 | B(001)→F(101)→C(100) |
| C ↔ D | G | 110 | C(100)→G(110)→D(010) |
The 8th vertex 111 stays unused.
Step 3 — modify the flow table. Whenever a transition would have crossed a long path, redirect it through the matching intermediate. For example, B→D on input $w_2w_1=10$ now becomes B→E (next-state E in row B); E is set up so that with input still 10, E→D (next-state D in row E). The table grows to 7 rows but the new entries are all "transit cells" that aren't stable for any input.
Step 4 — derive the excitation table. With 3 state variables $y_3 y_2 y_1$, write the next-state codes $Y_3 Y_2 Y_1$ for every (state, input) cell using the assignment above. The excitation entries can then be K-mapped to obtain the next-state logic, which drives the three feedback loops back to the state-bit latches/flip-flops.
What problem 9.26 asks specifically:
Why this matters: race-free state assignments are mandatory in asynchronous design — if two state bits change simultaneously, the FSM may briefly visit an unintended cube vertex, which is itself a stable state in the wrong row, and the circuit can deadlock. By breaking every multi-bit transition into single-bit hops through transit states, only one bit ever changes at a time and races become impossible.
The circuit (Figure 9.76) realizes an asynchronous FSM with state variables $y_1, y_2$, inputs $w_1, w_2$, output $z$. Logic: $Y_1 = w_1\overline{w_2} + \overline{w_2}\,y_1 + w_1 y_1 \overline{y_2}$, $Y_2 = w_2 + w_1 y_1 + w_1 y_2$, $z = y_2$.
Step 1 — build the excitation table. For each combination of $(y_2 y_1, w_2 w_1)$, evaluate the next-state codes $(Y_2 Y_1)$ and the output $z$:
| $y_2 y_1$ \ $w_2 w_1$ | 00 | 01 | 10 | 11 | $z$ |
|---|---|---|---|---|---|
| 00 | 00 | 01 | 10 | 10 | 0 |
| 01 | 01 | 01 | 10 | 11 | 0 |
| 10 | 00 | 10 | 10 | 10 | 1 |
| 11 | 11 | 11 | 10 | 11 | 1 |
Step 2 — identify stable states. A cell is stable iff $(Y_2 Y_1) = (y_2 y_1)$ for that input. Mark them (bold below in Figure 9.77's flow-table form). Each row corresponds to a present-state code.
Step 3 — name the states. Replace each binary code with a letter: $A = 00$, $B = 01$, $C = 10$, $D = 11$. Then:
| State | 00 | 01 | 10 | 11 | $z$ |
|---|---|---|---|---|---|
| A (00) | A | B | C | C | 0 |
| B (01) | B | B | C | D | 0 |
| C (10) | A | C | C | C | 1 |
| D (11) | D | D | C | D | 1 |
Step 4 — check for safe-race transitions. A "race" occurs when both state variables change simultaneously in response to one input change. From the excitation table, identify cells where both $Y_2$ and $Y_1$ differ from the present $y_2$ and $y_1$. Examples:
Definition: safe race. A race is "safe" (non-critical) if the FSM eventually settles in the correct stable state regardless of which state variable changes first. A race is critical (unsafe) if intermediate states are stable for the same input — the circuit may get stuck. The textbook usually solves the analysis problem by tabulating each multi-bit transition and verifying that all single-bit-change paths converge to the same destination.
What problem 9.31 asks:
f = x₁x₂ + x̄₂x₃ when x₁=x₃=1 and x₂ changes from 1 to 0. How can it be eliminated?f(x₁,x₂,x₃) = Σm(1,2,3,5,7) requires an additional product term beyond the minimum SOP. Identify the required term using a K-map.Y₁ = x̄₁(x₂ + y₁) and Y₂ = x₁(x̄₂ + y₂). Derive the flow table and identify all stable states.Spec. Asynchronous FSM with two inputs $D$ (dime sensed) and $N$ (nickel sensed). Output $z=1$ when at least 10 ¢ has been collected (dispense). 15 ¢ overpay gives no change. Asynchronous-design rule: only one input variable may change at a time, so $DN=11$ is unreachable.
Six-state initial state diagram (Moore-type, Figure 9.26a):
Primitive flow table (Figure 9.26b) — one stable state per row (bold = stable); dashes are don't-cares (forbidden $DN=11$ and impossible-transition entries):
| State | $DN$=00 | =01 | =10 | =11 | $z$ |
|---|---|---|---|---|---|
| A | A | B | C | — | 0 |
| B | D | B | — | — | 0 |
| C | A | — | C | — | 1 |
| D | D | E | F | — | 0 |
| E | A | E | — | — | 1 |
| F | A | — | F | — | 1 |
What the problem asks (two-step reduction):
Result (Figure 9.27 in the textbook). The 4 surviving states correspond to {idle, 5 ¢ collected with sensor cleared, 5 ¢ with sensor active, ≥10 ¢ collected}. Stable-state pairs that originally distinguished "10 ¢ via single dime" vs "10 ¢ via 5+5" merge because the asynchronous output and stable-state behavior are identical from that point on.
Why primitive tables are reducible: the one-stable-per-row format is verbose by construction. Many of those rows turn out to be doing the same thing once you allow don't-cares to be filled in. The two-step partition-then-merge procedure is the canonical asynchronous-FSM reduction algorithm.
Figure 9.52a — original 4-state Moore flow table (bold = stable, "—" = unspecified):
| State | $w_2 w_1$=00 | =01 | =10 | =11 | $z_2 z_1$ |
|---|---|---|---|---|---|
| A | A | B | C | A | 00 |
| B | B | B | D | C | 01 |
| C | A | C | D | C | 10 |
| D | B | — | D | A | 11 |
Counting stable-state cells: A×2, B×2, C×2, D×1 → 7 stable instances.
Figure 9.52b — relabeled with stable-instance numbers 1–7 (each stable cell gets a unique label so we can name transitions by their destination):
| State | 00 | 01 | 10 | 11 |
|---|---|---|---|---|
| A | 1 | 4 | 7 | 2 |
| B | 3 | 4 | 7 | 6 |
| C | 1 | 5 | 7 | 6 |
| D | 3 | — | 7 | 2 |
Why the relabeling helps: a transition like "C → A" in column 00 ends at the stable cell labeled 1 — so we annotate that arrow with "1". Multiple transitions ending at the same stable instance can share a label.
Step 1 — first transition diagram (assignment A=00, B=01, C=11, D=10). Connect every pair of states that exchange transitions; the offending arrows are diagonals on the 2-cube (Hamming distance 2):
Label-7 paths (transitions to stable D) have alternative routes via other states — they can be re-routed off the diagonal. But labels 1 and 3 are stuck on diagonals — no alternate path. So this assignment fails.
Step 2 — try swapping B and C codes (A=00, B=11, C=01, D=10). Now A↔B is the diagonal and B↔D becomes adjacent. Recheck:
Step 3 — exploit the unspecified entry. Row D, column 01 is "—". Fill it with $B$ (so D becomes a "pass-through" for the 01-input). Now the transition $A \to B$ on input 01 can be re-routed as $A \to D \to B$ (two single-bit hops: 00→10→11). The diagonal A↔B disappears from the transition graph because nobody needs it any more.
Augmented transition diagram (Figure 9.53c):
All edges are single-bit changes. The 2-cube embedding works → state assignment A=00, B=11, C=01, D=10 is race-free.
Why a Mealy model is needed afterward. Several transitions now route through unstable intermediate states (e.g., A→D→B). If the output were strictly $f(\text{state})$ (Moore), the FSM would briefly show D's output (11) while passing through it on the way to B (whose output is 01). That's an output glitch. To suppress glitches, the modified flow table (Figure 9.54a) re-specifies the output column-by-column as a function of $(\text{state}, w)$: in unstable cells, the output is forced to match the eventual stable destination's output, not the unstable transition state's output.
The general technique:
Same FSM as in problem 9.26 (Figure 9.55), where the 4-state transition diagram has all 6 state-pairs requiring transitions and can't embed on a 2-cube.
Figure 9.55a — flow table (stable states underlined; output $z_2 z_1$):
| state | $w_2w_1{=}00$ | $01$ | $10$ | $11$ | $z_2z_1$ |
|---|---|---|---|---|---|
| A | A | A | C | B | 00 |
| B | A | B | D | B | 01 |
| C | C | B | C | D | 10 |
| D | C | A | D | D | 11 |
Every pair of states has at least one transition (the diagram is $K_4$), so any 2-bit assignment forces at least one Hamming-2 step — that's the diagonal edge. Adding a third state-bit gives a 3-cube with 8 vertices, and the trick is to use those extra vertices to break the diagonals into single-bit hops.
Problem 9.26 solves it by inserting 3 extra unstable states (E, F, G). This problem solves it differently: replicate each of the 4 states as an equivalent pair, giving 8 states total — exactly enough to fill the 8 vertices of a 3-cube.
The state-splitting recipe:
Sample assignment that works: $A=000$, $A'=001$, $B=011$, $B'=010$, $C=110$, $C'=111$, $D=101$, $D'=100$. Walk the cube vertices in Gray-code order — each consecutive pair differs by one bit, so every "long" diagonal in the original 4-state graph can be replaced by routing to the appropriate clone of the destination.
Concrete example: A→B normally requires a 2-bit jump. Instead, route A=000 → A'=001 (1-bit) → B=011 (1-bit) → B'=010 (1-bit). The transit goes through a clone (A') and lands in the right state's clone (B'). Outputs match, so the user never knows which clone they're in.
Trade-off vs. the unstable-state approach (problem 9.26):
| Approach | Total states | Stable rows | Excitation logic |
|---|---|---|---|
| Insert E, F, G as transit (9.26) | 7 | 4 (original) | 3 transit cells per state — moderate complexity |
| Split each state into pair (9.27) | 8 | 8 (each original split) | Cleaner symmetry; uses every cube vertex |
What 9.27 specifically asks:
When to choose which approach: state-splitting tends to give simpler next-state logic (the symmetry helps K-map minimization), but doubles the row count and uses all cube vertices. Insertion of unstable transit states (9.26) has fewer rows but the transit cells are explicit "non-stable" places that must be carefully verified to never permanently latch.
Figure 9.65a — the POS circuit: $f = (x_1 + x_2)(\overline{x_2} + x_3)$ realized as two OR gates feeding an AND gate. Internal nodes $p = x_1 + x_2$ and $q = \overline{x_2} + x_3$.
The hazard scenario. Set $x_1 = x_3 = 0$ and toggle $x_2$ from 0 to 1. The function should stay at $f = 0$ throughout (both inputs to the AND cannot simultaneously be 1 in steady state):
| $x_2$ | $p = x_1 + x_2$ | $q = \overline{x_2} + x_3$ | $f = p \cdot q$ |
|---|---|---|---|
| 0 (steady) | 0+0 = 0 | 1+0 = 1 | 0·1 = 0 ✓ |
| 1 (steady) | 0+1 = 1 | 0+0 = 0 | 1·0 = 0 ✓ |
The glitch. During the $x_2: 0 \to 1$ transition, $p$ rises from 0 to 1 (the OR sees $x_2$ go up) before $q$ falls from 1 to 0 (because the inverter on $\overline{x_2}$ adds an extra delay before the second OR sees the change). For a brief window $p = q = 1$, so $f = 1$. The output exhibits a $0 \to 1 \to 0$ glitch — a static-0 hazard.
Why POS circuits hazard on adjacent 0s. In a POS circuit, the AND of OR-terms produces 0 only when at least one OR-term is 0. A hazard occurs at the boundary between two K-map 0-cells where no single sum-term covers both — momentarily both terms can be 1, giving $f = 1$.
The fix. Add a redundant sum-term $(x_1 + x_3)$ that covers both adjacent 0-cells (it is 0 only when $x_1 = x_3 = 0$). With this extra term, every transition between adjacent 0s leaves at least one OR-term at 0 throughout the transition:
$$f_{\text{hazard-free}} = (x_1 + x_2)(\overline{x_2} + x_3)(x_1 + x_3)$$Cost of removing the hazard: one extra OR2 gate plus one input to the AND. The extra gate is logically redundant — it does not change the function — but it bridges the gap that allowed the glitch.
Dual rule (memorize):
Figure 9.81 — original 8-row primitive flow table (Moore-type, output $z$ depends only on state):
| State | $w_2 w_1$=00 | =01 | =10 | =11 | $z$ |
|---|---|---|---|---|---|
| A | A | E | C | — | 0 |
| B | — | E | H | B | 1 |
| C | G | — | C | F | 0 |
| D | A | D | — | B | 1 |
| E | G | E | — | B | 0 |
| F | — | D | C | F | 0 |
| G | G | E | C | — | 0 |
| H | A | — | H | B | 1 |
Stage 1 — Partitioning by output groups (refine until stable):
$$P_1 = (ACEFG)(BDH) \qquad P_2 = (AG)(B)(C)(D)(E)(F)(H) \qquad P_3 = P_2$$Equivalence found: $A \equiv G$. Merge them into a single state (call it $A$). Result: 7-row table (Figure 9.82).
Stage 2 — Merger diagram on the 7-row reduced table identifies these compatible-pair merges:
After merging: 4-state table (Figure 9.84). Relabel for state assignment.
Stage 3 — State assignment. The relabeled 4-state transition diagram (Figure 9.86a) has one diagonal: D→A on some input, labeled "1" — Hamming-2 jump.
The fix: exploit a don't-care entry to route the diagonal D→A through state C (Hamming-1 hops): $D \to C \to A$. After this re-routing (Figure 9.86b), the transition diagram has no diagonals and embeds onto a 2-cube. State assignment becomes simply $A=00, B=01, C=11, D=10$ (or similar Gray-code mapping).
Stage 4 — Excitation table. With the assignment fixed, write next-state codes $(Y_2 Y_1)$ for every (state, input) cell. K-map the columns to derive logic for $Y_1$ and $Y_2$. Output $z$ is a function of state alone (Moore), so it K-maps directly from the present-state bits.
The full pipeline summary:
| Stage | Operation | Rows after |
|---|---|---|
| 0 | Original primitive flow table | 8 |
| 1 | Partitioning ($A \equiv G$) | 7 |
| 2 | Merger diagram (A+E, C+F, D+H) | 4 |
| 3 | State assignment + diagonal-routing fix | 4 (no change in count) |
| 4 | Excitation table → K-maps → next-state logic | — |
What problem 9.34 specifically asks: walk through stages 1–4 above, preserving the Moore model throughout (so the merger constraint is "same output in stable cells", not the looser Mealy compatibility).