Recap of Example 5.3 (blocking — wrong for cascading). The textbook starts with this code:

module example5_3 (D, Clock, Q1, Q2);
  input D, Clock;
  output reg Q1, Q2;
  always @(posedge Clock) begin
    Q1 = D;     // blocking
    Q2 = Q1;    // blocking — Q1 already updated
  end
endmodule

Blocking assignments evaluate sequentially. After Q1 = D;, the variable Q1 already holds the new value D, so Q2 = Q1; reads D as well. Both FFs latch the same input on every clock edge:

Problem 5.16 — non-blocking (right): swap = for <=:

always @(posedge Clock) begin
  Q1 <= D;     // non-blocking
  Q2 <= Q1;    // reads OLD Q1 (value at block entry)
end

Non-blocking assignments all sample their right-hand sides at the moment the always block fires, then commit new values together at the end. So Q2 <= Q1; reads the previous value of Q1 — exactly what a real cascaded FF does. The synthesized hardware is a true 2-stage shift register:

Side-by-side semantics for one rising edge. Suppose before the edge: $D=1, Q_1=0, Q_2=0$.

After the second clock edge with non-blocking, $Q_2$ finally becomes 1 — the input has propagated through two stages, hence "shift register".

Rule of thumb. Use non-blocking (<=) for everything inside a clocked always @(posedge clk) block. Use blocking (=) only in combinational always @(*) blocks where sequential evaluation matches gate-level dataflow. Mixing the two in the same block is the most common source of synthesis-vs-simulation mismatches.

Four requirements:

1. parameterized Verilog module regn — module name is regn ("register, parameterized n"). Must use Verilog's parameter mechanism so the bit width is not hard-coded — the same module file works for any width by passing a different value at instantiation.

2. for an $n$-bit register — a bank of $n$ D flip-flops in parallel: input bus D[n-1:0], output bus Q[n-1:0], one shared clock. On each rising clock edge, the $n$ inputs latch into the $n$ outputs simultaneously.

3. with asynchronous clear — a reset signal that clears all $n$ bits to 0 immediately when asserted, not waiting for the next clock edge. Implementation-wise, the reset signal goes into the always-block sensitivity list along with the clock (always @(posedge Clock or negedge Resetn)), so the block fires the moment reset asserts. Contrast: a synchronous clear would only take effect on the next rising clock edge.

4. where $n$ is a parameter with a default value:

• n declared with parameter (not localparam, not a hard-coded number).
• Default value provided so instantiating without specifying width gets a sensible fallback (e.g., 8 bits).

What the grader checks: one module file that supports regn r1(); (default), regn #(.n(16)) r2(); (16-bit), regn #(32) r3(); (32-bit) — all without editing the source. Asserting Resetn drops Q to 0 between clock edges (visible in waveform). All $n$ bits load D on the rising clock edge when Resetn is inactive.

A muxdff is the workhorse cell of a parallel-load / shift register: a single D flip-flop preceded by a 2-to-1 multiplexer that selects between two next-state values. The MUX's select line is usually called L (load):

• L = 0 — MUX picks the "shift" input w; the FF clocks in the bit coming from a neighbour cell. The chain shifts.
• L = 1 — MUX picks the "parallel" input R; the FF clocks in a fresh data bit from outside. The register loads.

It's the smallest building block that lets a register do both jobs (shift OR load) under a single control bit.

Verilog for the muxdff cell:

module muxdff (
  input  R, w, L, Clock,
  output reg Q
);
  always @(posedge Clock)
    Q <= L ? R : w;   // L=1 → load R; L=0 → shift in w
endmodule

Building a 4-bit parallel-load shift register by chaining four muxdff cells:

Each cell's MUX bottom input is wired to the previous cell's Q. With L=0, bits ripple through the chain (shift). With L=1, every cell loads its corresponding R[i] in parallel.

Hierarchical Verilog (problem 5.22's task):

module shift_load_4 (
  input  [3:0] R,
  input        L, w, Clock,
  output [3:0] Q
);
  muxdff bit3 (.R(R[3]), .w(w),    .L(L), .Clock(Clock), .Q(Q[3]));
  muxdff bit2 (.R(R[2]), .w(Q[3]), .L(L), .Clock(Clock), .Q(Q[2]));
  muxdff bit1 (.R(R[1]), .w(Q[2]), .L(L), .Clock(Clock), .Q(Q[1]));
  muxdff bit0 (.R(R[0]), .w(Q[1]), .L(L), .Clock(Clock), .Q(Q[0]));
endmodule

Why the muxdff abstraction matters: almost every register in a real design needs more than just "clock D into Q on each edge". Adding load, shift, hold, and reset capabilities can pile up ifs and edge cases. Capturing each combination as a tiny named cell (muxdff, plus enable/reset variants) and instantiating n copies for an n-bit register is the cleanest way to scale — verify the cell once, reuse everywhere.

Figure 5.70a — two cascaded inverters tap-off internal nodes A and B

So $A = \overline{C}$ delayed by $\Delta$, and $B = C$ delayed by $2\Delta$ (i.e. $A$ further inverted).

The circuit. Two edge-triggered JK flip-flops share clock input $w$ and a common asynchronous Clear. Both K inputs are tied to logic 1, so each FF either holds (when $J=0$) or toggles (when $J=1$). The combinational wiring is:

• $J_0 = \overline{Q_1}$, $K_0 = 1$  (FF0 toggles unless $Q_1=1$, in which case it resets)
• $J_1 = Q_0$,  $K_1 = 1$  (FF1 toggles when $Q_0=1$, otherwise resets)

JK behavior recap. On each rising edge of $w$:

State walk-through. Start from Clear $\Rightarrow Q_1Q_0=00$:

The cycle closes after three pulses: $00 \to 01 \to 10 \to 00 \to \ldots$ — exactly the count sequence 0, 1, 2, 0, 1, 2, … so the circuit is a modulo-3 (divide-by-3) counter.

Timing diagram (matches Figure 5.72; both FFs are positive-edge-triggered on $w$):

Why this wiring works. State $11$ is excluded by construction: from state $10$, $J_0=\overline{Q_1}=0$ keeps $Q_0$ at 0, so the next state can never be $11$. With only three reachable states, three clock pulses return to the start — the defining property of a mod-3 counter.

Connection to Chapter 6. This is a hand-crafted FSM. In §6.7 the same mod-3 counter is re-derived systematically: pick a state assignment, build the excitation table for JK FFs (using the inverse of the JK characteristic table), and read $J_i$, $K_i$ off K-maps. The wiring above is the optimal result of that procedure.