This chapter covers how numbers are stored and manipulated in digital systems. It begins with positional number representations including unsigned integers, octal, and hexadecimal. The half-adder and full-adder are derived and combined to build ripple-carry adders. Signed number systems are introduced: sign-and-magnitude, 1's complement, and 2's complement (the standard for modern computers). The chapter covers addition, subtraction, arithmetic overflow detection, and fast adder designs including the carry-lookahead adder. Array multiplication and Booth's algorithm concepts are presented. Fixed-point, floating-point (IEEE 754), and BCD representations are also discussed. A significant portion of the chapter demonstrates how to describe all of these arithmetic circuits in Verilog using vectored signals, generic specifications, and arithmetic assignment statements.
Convert the hexadecimal number $\text{3F7A}$ to binary and then to decimal.
3.2EasyTier 1?R✓
Convert the decimal numbers 73, −95, and −1630 into signed 12-bit numbers in sign-and-magnitude, 1's complement, and 2's complement representations.
3.3EasyTier 1?R✓
Draw the circuit for a half-adder. Label all signals and write the truth table.
3.4MediumTier 1?R✓
Perform the following 8-bit 2's complement additions and indicate whether overflow occurs: $00110110 + 01000101$, $01110101 + 11011110$, $11011111 + 10111000$.
3.5MediumTier 1?R✓
Show that the overflow condition for adding two n-bit 2's complement numbers is $\text{Overflow} = c_n \oplus c_{n-1}$, where c represents the carry signals.
3.6MediumTier 1?R✓
Design a 4-bit ripple-carry adder using full-adder blocks. Draw the block diagram showing all carry connections.
3.7MediumTier 1?R✓
Show how a 4-bit adder can be modified into an adder/subtractor unit using XOR gates and a control signal Sub.
3.8MediumTier 1?R✓
Multiply the 4-bit unsigned numbers $1101$ and $1011$ using the array (partial product) method. Show all partial products.
3.9MediumTier 1?R✓
Represent the decimal number $-6.5$ in IEEE 754 single-precision floating-point format. Show the sign, exponent, and mantissa fields.
3.10MediumTier 1?R✓
Write a Verilog module for a parameterized n-bit ripple-carry adder using a generate statement to instantiate n full-adder modules.
3.11MediumTier 1?R✓
Explain why the simple rule for finding the 2's complement works: "scanning right to left, copy all 0s and the first 1, then complement all remaining bits."
3.12MediumTier 1?R✓
What is the range of representable values for an 8-bit number in sign-and-magnitude, 1's complement, and 2's complement? How many unique values does each represent?
3.13MediumTier 1E?R✓
Show that for $n$-digit decimal numbers $A$ and $B$, the subtraction $A-B$ can be done as $A+(10^n-B)-10^n$. Explain how the carry-out from the leading digit corresponds to discarding $10^n$, and what happens when $A < B$.
3.14MediumTier 1E?R✓
Using 3-digit signed decimal numbers (with leading 0 for positive and 9 for negative), compute $045 - 027$ and $027 - 045$ via the 10's-complement add-and-discard-carry technique. Verify that the second result is the 10's complement of $-18$.
3.15EasyTier 1E?R✓
Using 4-bit 2's complement and the add-and-discard-carry method, compute $(+5)-(+2)$. Confirm that the carry from the fourth bit position represents $2^4$ and can be ignored.
3.16EasyTier 1E?R✓
Using 4-bit 2's complement, compute $(+2)-(+5)$ via the add-and-discard-carry method. Verify that the result $1101$ is the 2's complement representation of $-3$.
3.17EasyTier 1E?R✓
Using 4-bit 2's complement, compute $(+5)-(-2)$ by the add-and-discard-carry technique. Verify the result is $0111 = +7$.
3.18EasyTier 1E?R✓
Convert the decimal integer $14959$ into hexadecimal by successive division by 16, recording each remainder as a hex digit.
3.19EasyTier 1E?R✓
Convert the decimal fraction $0.8254$ into a binary fraction with at least eight bits after the radix point, using successive multiplication by 2.
3.20MediumTier 1E?R✓
Convert the decimal fixed-point number $214.45$ into a binary fixed-point number, performing successive division by 2 for the integer part and successive multiplication by 2 for the fractional part.
3.21MediumTier 1E?R✓
A 4-bit comparator is built from a 2's-complement subtractor that outputs $S = X - Y$ along with three flags: $Z=1$ if $S=0$, $N=1$ if $S$ is negative, $V=1$ on overflow. Derive expressions in terms of $Z, N, V$ for each of $X=Y$, $X \lt Y$, $X \le Y$, $X \gt Y$, $X \ge Y$.
3.22MediumTier 1E?R✓
Write Verilog code for the 4-bit signed comparator of Example 3.9. Provide both a structural version that instantiates four full-adder modules and a generic version using a parameter $n$ and a for loop.— example 3.9
3.23HardTier 1E?R✓
Compare the critical-path delay of a 4-bit ripple-carry array multiplier (Figure 3.35) with that of a 4-bit carry-save array multiplier (Figure 3.48). Express each delay as a multiple of the full-adder delay plus the AND-gate delay.Context: Figures 3.35 & 3.48 — ripple-carry vs carry-save 4-bit multipliers
Both circuits multiply two 4-bit unsigned numbers $M = m_3 m_2 m_1 m_0$ and $Q = q_3 q_2 q_1 q_0$ to produce an 8-bit product $P = p_7 \ldots p_0$. They use the same partial-product generation (16 AND gates: $m_i q_j$) but differ in how the sums are accumulated.
Figure 3.35 — ripple-carry array (slow): FAs in each row are chained left-to-right with the carry-out of one feeding the carry-in of the next (ripple). Then the row's sum bits drop into the next row, which again ripples. The critical path snakes through several rows.
Walk the critical path right-to-left through row 1 (2 FAs) → row 2 (2 FAs) → row 3 → row 4 (whole bottom ripple, 4 FAs) → exit at the leftmost product bit. 8 FA delays + 1 AND delay total.
Figure 3.48 — carry-save array (fast): within each of the first three rows, carries are saved (sent to the next row at the correct bit position) instead of rippled. Each FA in rows 1–3 thus sees three independent shifted partial-product bits. The bottom row is still a 4-FA ripple-carry adder to merge the final saved carries with the running sum.
Walk the critical path: rightmost FA in row 1 → rightmost FA in row 2 → straight down to row 4 (no horizontal ripple in row 3 thanks to carry-save) → all 4 FAs of the bottom ripple-carry adder. 6 FA delays + 1 AND delay total — a savings of 2 FA delays (25 % faster).
Comparison:
Architecture
Critical path FAs
Total delay
Ripple-carry array (Fig 3.35)
2 + 2 + 4 = 8
$8\,t_{FA} + t_{AND}$
Carry-save array (Fig 3.48)
1 + 1 + 4 = 6
$6\,t_{FA} + t_{AND}$
Why carry-save is faster: in rows 1–3, sums and saved carries propagate only vertically, not horizontally. Each FA waits one delay regardless of which column it sits in. Only the final adder row needs to ripple. For an $n \times n$ multiplier the ripple-carry array delay is $\mathcal{O}(n)$ rows × $\mathcal{O}(n)$ ripple per row = $\mathcal{O}(n^2)$ FA-delays in the worst case (ish), while the carry-save form is $\mathcal{O}(n)$ — the basis of all modern fast multipliers (Wallace tree, Dadda multiplier, etc.).